• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
• /
• pp.1368-1371
• /
• 2007

Laser-ablated ITO patterns showed the formation of shoulders at the edge of the ITO lines and a ripple-like structure of the etched bottom. When the laser ablation was applied in the fabrication of PDP panel, the laser-ablated ITO patterns showed a higher sustaining voltage than that of chemically wet-etched ITO.

• 한국막학회:학술대회논문집
• /
• 한국막학회 1997년도 추계 총회 및 학술발표회
• /
• pp.141-142
• /
• 1997

1. 서론 : 중공사막은 제조과정인 wet spinning의 과정에서 defect가 형성될 수 있어 분리선택도에 큰 영향을 미친다. 이러한 defect의 처리방법으로는 dipping method등의 방법이 현재 널리 쓰이고 있다. dipping method는 제조된 중공사막을 PDMS등의 고분자 용액 속으로 통과시켜 결과적으로 중공사막 표면에 얇은 고분자막이 형성되도록 하는 방법이다. 그러나 이러한 방법으로 중공사막을 처리할 경우 고분자 용액이 pore내로 침입하거나 중력으로 인하여 용액의 아래쪽으로 몰려 하반부의 두께가 두꺼워진다는 단점이 있다.(생략)

• 한국인터넷방송통신학회논문지
• /
• 제20권3호
• /
• pp.135-140
• /
• 2020

반도체 공정에서 필수적인 공정가스가 유해가스이기 때문에 이를 친환경적으로 해결하는 것이 필수과제이다. 현재 반도체 공정에서 사용되는 세정기술은 대부분이 1970년대 개발된 과산화수소를 근간으로 하는 습식 세정으로, 표면의 입자를 제거하기 위한 SC-1 세정액은 암모니아와 과산화수소 혼합액을 사용하고 있다. 따라서 환경적 문제를 유발하며, 또한 과도한 용수 사용으로 인한 경제적 문제도 심각하다. 이러한 이유로 본 연구를 통한 개발 제품은 챔버 출구에서 나오는 공정 유해가스를 진공펌프에 입력되기 전 가스를 분해하여 해가 없는 가스로 만들거나 소각과 동시에 펌프에 가스의 성분이 증착되어 반도체 공정의 환경적 문제를 해결하고자 한다. 본 논문에서는 반도제 공정에서 필수 불가결하게 사용되는 유해가스(N2, CF4, SF6⋯. 등)를 사람에게 무해한 가스로 치환하거나 플라스마로 소각하여 환경을 살리고 생산성 향상이 되도록 제안된 CPS (Confined Plasma Source)를 연구하고자 한다.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
• /
• pp.1038-1041
• /
• 2003

In the paper, we investigated silicon surface microstructures formed by reactive ion etching in hollow cathode system. Wet anisotropic chemical etching technique use to form random pyramidal structure on <100> silicon wafers usually is not effective in texturing of low-cost multicrystalline silicon wafers because of random orientation nature, but High density hollow cathode plasma system illustrates high deposition rate, better film crystal structure, improved etching characteristics. The etched silicon surface is covered by columnar microstructures with diameters form 50 to 100nm and depth of about 500nm. We used $SF_{6}$ and $O_{2}$ gases in HCP dry etch process. This paper demonstrates very high plasma density of $2{\times}10^{12}$ $cm^{-3}$ at a discharge current of 20 mA. Silicon etch rate of 1.3 ${\mu}s/min$. was achieved with $SF_{6}/O_{2}$ plasma conditions of total gas pressure=50 mTorr, gas flow rate=40 sccm, and rf power=200 W. Our experimental results can be used in various display systems such as thin film growth and etching for TFT-LCDs, emitter tip formations for FEDs, and bright plasma discharge for PDP applications. In this paper we directed our study to the silicon etching properties such as high etching rate, large area uniformity, low power with the high density plasma.

• 한국표면공학회:학술대회논문집
• /
• 한국표면공학회 2012년도 추계총회 및 학술대회 논문집
• /
• pp.171-171
• /
• 2012

In this study, we fabricated the high-brightness AlGaInP-based red light emitting diodes (LED)s using by direct printing technique and inductive coupled plasma (ICP) reactive ion etching (RIE). In general, surface roughening was fabricated by wet etching process to improve the light extraction efficiency of AlGaInP-based red LED. However, a structure of the surface roughening, which was fabricated by wet etching, was tiled cone-shape after wet etching process due to crystal structure of AlGaInP materials, which was used as top-layer of red LED. This tilted cone-shape of surface roughening can improve the light extraction of LED, but it caused a loss of the light extraction efficiency of LED. So, in this study, we fabricated perfectly cone shaped pattern using direct printing and dry etching process to maximize the light extraction efficiency of LED. Both submicron pattern and micron pattern was formed on the surface of red LED to compare the enhancement effect of light extraction efficiency of LEDs according to the diameter of sapphire patterns.After patterning process using direct printing and ICP-RIE proceeded on the red LED, light output was enhanced up to 10 % than that of red LED with wet etched structure. This enhancement of light extraction of red LED was maintained after packaging process. And as a result of analyze of current-voltage characteristic, there is no electrical degradation of LED.

• 한국진공학회지
• /
• 제8권4A호
• /
• pp.490-495
• /
• 1999

In 0.18 $\mu \textrm m$ LOGIC device, the etch rate of NMOS polysilicons is different from that of PMOS polysilicons due to the state of polysilicon to manufacture gate line. To control the etch profile, we tested the ratio of $Cl_2$/HBr gas and the total chamber pressure, and also we reduced Back He pressure to get the vertical profile. In the case of manufacturing the gate photoresist line, we used Bottom Anti-Reflective Coating (BARC) to protect refrection of light. As a result we found that $CF_4O_2$ gas is good to etch BARC, because of high selectivity and good photoresist line profile after etching BARC. in the results of the characterization of plasma damage to the antenna effect of gate oxide, NO type thin film(growing gate oxide in 0, ambient followed by an NO anneal) is better than wet type thin film(growing gate oxide in $0_2+H_2$ ambient).

• 한국분말재료학회지
• /
• 제19권1호
• /
• pp.6-12
• /
• 2012

Electricity is generated by the combined reactions of hydrogen oxidation and oxygen reduction which occur on the Pt/C catalyst surface. There have been lots of researches to make high performance catalysts which can reduce Pt utilization. However, most of catalysts are synthesized by wet-processes and a significant amount of chemicals are emitted during Pt/C synthesis. In this study, Pt/C catalyst was produced by arc plasma deposition process in which Pt nano-particles are directly deposited on carbon black surfaces. During the process, islands of Pt nano-particles were produced and they were very fine and well-distributed on carbon black surface. Compared with a commercialized Pt/C catalyst (Johnson & Matthey), finer particle size, narrower size distribution, and uniform distribution of APD Pt/C resulted in higher electrochemical active surface area even at the less Pt content.

• 한국표면공학회:학술대회논문집
• /
• 한국표면공학회 2008년도 추계학술대회 초록집
• /
• pp.90-90
• /
• 2008

실리콘을 기판으로 하는 대부분의 태양전지에서는 표면반사에 의한 광에너지손실을 최소화시키고자 습식에칭(wet etching)에 의한 텍스쳐링처리가 이루어진다. 그러나 습식 에칭은 공정 과정이 번거롭고 비용이 많이 든다. Inductively Coupled Plasma Etcher 장비를 이용한 플라즈마 에칭 (plasma etching)을 실리콘 표면에 적용하여 공정을 간단하고 저렴하게 하며 반사도를 획기적으로 낮추는 기술이 개발되었다. 습식 에칭으로 형성된 표면의 피라미드 구조는 1차 반사 후 빛의 일부가 외부로 흩어져 나가지만 플라즈마 에칭으로 형성된 나노구조는 내부전반사가 가능하여 대부분의 태양 에너지를 흡수한다. 나노구조는 필라(pillar)의 형태로 형성되며 이 필라의 길이에 따라 반사도가 다르게 나타난다. 이는 플라즈마 에칭 시 발생하는 이온폭격과 에칭 측벽 식각 보호막(SiOxFy : Silicon- Oxy- Fluoride)이 필라의 길이에 영향을 주기 때문이며, 필라가 길수록 반사도를 저하시킨다. 최저의 반사도를 얻기 위해서 나노필라 형성에 기여하는 플라즈마 에칭 시간, RF bias power, SF6/O2 gas ratio의 변화에 따른 실험이 진행되었다. 플라즈마 발생 초기에는 표면의 거칠기만 증가할 뿐 필라가 형성되지 않지만 특정조건에서 3um 이상의 필라를 얻는다. 이는 에칭 측벽 식각 억제막이 약한 부분으로 이온폭격이 집중되어 발생한다. 플라즈마 에칭을 적용하여 형성된 나노필라는 반사도가 가시광 영역에서 대략 1%에 불과하며, 마스크 없이 공정이 가능한 장점이 있다.

• 한국신재생에너지학회:학술대회논문집
• /
• 한국신재생에너지학회 2005년도 춘계학술대회
• /
• pp.192-195
• /
• 2005

The silicon thin film solar cells were fabricated by 13.56 MHz PECVD (Plasma-Enhanced Chemical-Vapor Deposition) and 60 MHz VHF PECVD (Very High-Frequency Plasma-Enhanced Chemical-Vapor Deposition). We focus on textured ZnO:Al films prepared by RF sputtering and post deposition wet chemical etching and studied the surface morphology and optical properties. These films were optimized the light scattering properties of the textured ZnO:Al after wet chemical etching. Finally, the textured ZnO:Al films were successfully applied as substrates for silicon thin films solar cells. The efficiency of tandem solar cells with $0.25 cm^2$ area was $11.8\%$ under $100mW/cm^2$ light intensity. The electrical properties of tandem solar cells were measured with solar simulator (AM 1.5, $100 mW/cm^2)$ and spectral response measurements.

• 한국재료학회지
• /
• 제15권3호
• /
• pp.202-208
• /
• 2005

The surface states of gate dielectrics affect device performance severely in Pentacene OTFTs. We have fabricated organic thin-film transistors (OTFTs) using pentacene as an active layer with chemically modified $SiO_2$ gate dielectrics. The effects of the surface treatment of $SiO_2$ on the electric characteristics of OTFTS were investigated. The surface of $SiO_2$ gate dielectric was treated by normal wet cleaning process, $O_2-plasma$ treatment, hexamethyldisilazane (HMDS), and octadecyltrichlorosilane (OTS) treatment. After the surface treatments, the contact angles and surface free energies were measured in order to analyze the surface state changes. In the electrical measurements, typical I-V characteristics of TFTs were observed. The field effect mobility, $\mu$, was calculated to be $0.29\;cm^2V^{-1}s^{-1}$ for OTS treated sample while those for the HMDS, $O_2$ plasma treated, and wet-cleaned samples were 0.16, 0.1, and $0.04\;cm^2V^{-1}s^{-1}$, respectively.