• Journal of the Semiconductor & Display Technology
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• v.5 no.2 s.15
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• pp.47-49
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• 2006

Various methods of making thin film is being used in semiconductor manufacturing process. The most common method in this field includes CVD(Chemical Vapor Deposition) and PVD(Physical Vapor Deposition). Thin film is deposited on both the backside and the frontside of wafers. The thin film deposited on the backside has poor thickness profile, and can contaminate wafers in the following processes. If wafers with the thin film remaining on the backside are immersed in batch type process tank, the thin film fall apart from the backside and contaminate the nearest wafer. Thus, it is necessary to etch the backside of the wafer selectively without etching the frontside, and chemical injection nozzle positioned under the wafer can perform the backside etching. In this study, the backside chemical injection nozzle with optimized chemical injection profile is built for single wafer tool. The evaluation of this nozzle, performed on $Si_3N_4$ layer deposited on the backside of the wafer, shows the etching rate uniformity of less than 5% at the etching rate of more than $1000{\AA}$.

• Korean Journal of Materials Research
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• v.3 no.4
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• pp.352-360
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• 1993

A nitride layer was df'posited on the thermal oxide layer by LPCVD process. ONO(oxidenitricle oxide) capacitors with various thickness of component layer wore fabricated by wet reoxidation of the nitride with and without anrwalmg treatment and their properties were investigated. As a result of observation on the refrative index and etching behavior of the ONO fIlms, the nitride layer OF 40 A thick ness was not so dense that the bottom oxide during the reoxidation process and the capability of securing the capacitance decreased. The conduction current in the ONO multl-Iayer dielctric film was reduced as the bottom(or top) oxide layer became thicker. However, in the case of oxide with thickness more than 50A, it merely plays a factor of reduction in capacitance, and the effect of barrier for hole injection was not so much increased. Annealing of the nitride laypr bpfore reoxidation did not show a grpat effects on the refractive index and capacitance of the film, however, the annealing process increased the breakdown voltage by 2${\cdot}$V.

• Journal of the Korean Ceramic Society
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• v.34 no.2
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• pp.188-194
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• 1997

Wet gel with surface modification by TMCS was redispersed in EtOH and redispersed silica sol for coat-ing was prepared. After spin coating of redispersed sol was conducted on silicon substrate, processes of drying(8$0^{\circ}C$) and heat treatment(>25$0^{\circ}C$) were, followed at ambient pressure. The influence of heat treat-ment of properties of film was observed, changing temperature at heat treatment. The optimum redisp-ersion condition for stable silica sol was wet gel:EtOH=1g:110$m\ell$ and the concentration and viscosity of redispersed silica sol with average particle size of 30nm were 0.11 M, 2.0-2.2 cP respectively. Crack-free thin film with the refractive index of 1.14 and thickness of 400 nm was obtained through drying at 8$0^{\circ}C$ and subsequent heat treatment at 45$0^{\circ}C$ for 2 hrs respectively after spin coating of 1500rpm, 10 times.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.12
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• pp.1075-1079
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• 2005

The Pseudo MOSFET measurements technique has been used for the electrical characterization of the nano SOI wafer. Silicon islands for the Pseudo MOSFET measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo MOSFET were not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device were dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100 nm SOI was obtained by thinning the silicon film of standard thick SOI wafer. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching Process dependency is greater in the thinner SOI wafer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.3-4
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• 2005

The Pseudo-MOSFET measurements technique has been used for the electrical characterization of the nano SOL Silicon islands for the Pseudo-MOS measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo-MOS was not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device was dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100nm SOI was obtained by thinning the silicon film of standard thick SOI. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo-MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching process dependency is greater in the thinner SOI and related to original SOI wafer quality.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.912-915
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• 2004

Inductors material utilized in the downsizing passive devices and Rf components requires the physical and electrical properties at given area such as inductors thickness reduction, inductance and q-factor increase, low leakage current and thermal stability. In this study, Spiral inductors on the $SiO_2/Si$(100) substrate were fabricated by the magnetron sputtering method. Cu thin film with the thickness of $2{\mu}m$ was deposited on the substrate. Also we fabricated square inductors through the wet chemical etching technique. The inductors are completely specified by the turn width and the spacing between spirals. Both the width and spacing between spirals were varied from 10 to $60{\mu}m$ and from 20 to $70{\mu}m$, respectively. Inductance and Q factor dependent on the RF frequency were investigated to analyze performance of inductor arrays

• 한국초전도학회:학술대회논문집
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• v.15
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• pp.56-56
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• 2005

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.2105-2107
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• 2004

In this study, Spiral inductors on the $SiO_2$/Si(100) substrate were fabricated by the magnetron sputtering method. Cu thin film with the thickness of 2 ${\mu}m$ was deposited on the substrate. Also we fabricated square inductors through the wet chemical etching technique. The inductors are completely specified by the turn width and the spacing between spirals. Both the width and spacing between spirals were varied from 10 to 60 ${\mu}m$ and from 20 to 70 ${\mu}m$, respectively. Inductance and Q factor dependent on the RF frequency were investigated to analyze performance of inductor arrays. Also, We recommend that the reasonable Q-factors, spec's turns and thickness of the coil for inductors cab be set to be ideal condition.

• Journal of the Korean Vacuum Society
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• v.22 no.3
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• pp.131-137
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• 2013

The thin insulator films for organic memory device were made by the plasma polymerization method using the styrene monomer which was not the wet process but the dry process. For the formation of stable plasma, we make an effort for controlling the monomer with bubbler and circulator system. The thickness of plasma polymerized styrene insulator layer was 430 nm, the thickness of the Au memory layer was 7 nm thickness of plasma polymerized styrene tunneling layer was 30, 60 nm, the thickness of pentacene active layer was 40 nm, the thickness of source and drain electrodes were 50 nm. The I-V characteristics of fabricated memory device got the hysteresis voltage of 45 V at 40/-40 V double sweep measuring conditions. If it compared with the results of previous paper which was the organic memory with the plasma polymerized MMA insulation thin film, this result was greater than 18 V, the improving ratio is 60%. From the paper, styrene indicated a good charge trapping characteristics better than MMA. In the future, we expect to make the organic memory device with plasma polymerized styrene as the memory thin film.

• Journal of the Korean Vacuum Society
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• v.21 no.6
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• pp.354-361
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• 2012

The organic memory device was made by the plasma polymerization method which was not the dry process but the wet process. The memory device consist of the styrene and MMA monomer as the insulating layer, MMA monomer as the tunneling layer and Au thin film as the memory layer which was fabricated by thermal evaporation method. The I-V characteristics of fabricated memory device got the hysteresis voltage of 27 V at 40/-40 V double sweep measuring conditions. At this time, the optimized structure was 7 nm of Au thin film as floating gate, 400 nm of styrene thin film as insulating layer and 30 nm of MMA thin film as tunneling layer. Therefore we got the charge trapping characteristics by the hysteresis voltage. From the paper, styrene indicated a good charge trapping characteristics better than MMA. In the future, we expect to make devices by using styrene thin film rather than Au thin film.