• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.5
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• pp.475-480
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• 2017

In this paper, the conductivity of the fine pattern is improved in the insulating substrate by laser-induced forward transfer (LIFT) process. The high laser beam energy generated in conventional laser induced deposition processes induces problems such as low deposition density and oxidation of micro-patterns. These problems were improved by using a polymer coating layer for improved deposition accuracy and conductivity. Chromium and copper were used to deposit micro-patterns on silicon wafers. A multi-pulse laser beam was irradiated on a metal thin film to form a seed layer on an insulating substrate(SiO2) and electroless plating was applied on the seed layer to form a micro-pattern and structure. Irradiating the laser beam with multiple scanning method revealed that the energy of the laser beam improved the deposition density and the surface quality of the deposition layer and that the electric conductivity can be used as the microelectrode pattern. Measuring the resistivity after depositing the microelectrode by using the laser direct drawing method and electroless plating indicated that the resistivity of the microelectrode pattern was $6.4{\Omega}$, the resistance after plating was $2.6{\Omega}$, and the surface texture of the microelectrode pattern was uniformly deposited. Because the surface texture was uniform and densely deposited, the electrical conductivity was improved about three fold.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.3 s.36
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• pp.187-196
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• 2005

MEMS devices such as a vibratory gyroscope often suffer from a lower yield rate due to fabrication errors and the external stress. In the decoupled vibratory gyroscope, the main factor that determines the yield rate is the frequency difference between the sensing and driving modes. The gyroscope, fabricated with SOI (Silicon-On-Insulator) wafer and packaged using the anodic bonding, has a large wafer bowing caused by thermal expansion mismatch as well as non-uniform surfaces of the structures caused by the notching effect. These effects result in large distribution in the frequency difference, and thereby a lower yield rate. To improve the yield rate we propose a packaged SiOG (Silicon On Glass) technology. It uses a silicon wafer and two glass wafers to minimize the wafer bowing and a metallic membrane to avoid the notching. In the packaged SiOG gyroscope, the notching effect is eliminated and the warpage of the wafer is greatly reduced. Consequently the frequency difference is more uniformly distributed and its variation is greatly improved. Therefore we can achieve a more robust vibratory MEMS gyroscope with a higher yield rate.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.55-59
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• 2018

In this paper, we investigated the characteristics of shear stress type piezoresistor on a diaphragm structure formed by MEMS (Microelectromechanical System) technology of silicon-direct-bonding (SDB) wafers with Si/$SiO_2$/Si-sub. The diaphragm structure formed by etching the backside of the wafer using a TMAH aqueous solution can be used for manufacturing various sensors. In this study, the optimum shape condition of the shear stress type piezoresistor formed on the diaphragm is found through ANSYS simulation, and the diaphragm structure is formed by using the semiconductor microfabrication technique and the shear stress formed by boron implantation. The characteristics of the piezoelectric resistance are compared with the simulation results. The sensing diaphragm was made in the shape of an exact square. It has been experimentally found that the maximum shear stress for the same pressure at the center of the edge of the diaphragm is generated when the structure is in the exact square shape. Thus, the sensing part of the sensor has been designed to be placed at the center of the edge of the diaphragm. The prepared shear stress type piezoresistor was in good agreement with the simulation results, and the sensitivity of the piezoresistor formed on the $2200{\mu}m{\times}2200{\mu}m$ diaphragm was $183.7{\mu}V/kPa$ and the linearity of 1.3 %FS at the pressure range of 0~100 kPa and the symmetry of sensitivity was also excellent.

• Journal of Sensor Science and Technology
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• v.1 no.1
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• pp.23-34
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• 1992

In order to fabricate magnetoresistive sensor, Fe-Ni and Co-Ni alleys were evaporated on the slide glass and the silicon wafers. Saturation magnetic induction($B_{s}$), coercive field strength($H_{c}$) and magnetoresistance were measured for fabricated samples. The evaporated Fe-Ni thin films show that the saturation magnetic induction was 0.65 T, and coercive field strength was 0.379 A/cm, and this value was changed to 0.370 A/cm(//), 0.390 A/cm(${\bot}$), respectively after magnetic annealing. For the measurement of coercive field strength, magnetizing frequency of 1 kHz was used. For the fabricated sensor element, the change of magnetoresistance (${\Delta}R/R$) was excessively unstable due to oxidation in the process of fabrication. The evaporated Co-Ni alloy thin films show that saturation magnetic induction was 0.66 T, and coercive field strengthes were 5.895 A/cm(//), 5.898 A/cm(${\bot}$), respectively, after magnetic annelaing. The change of magnetoresistance(${\Delta}R/R$) was $3.6{\sim}3.7%$ of which value was excessively stable to room temperature. Fe-Ni thin film could have many problems due to large affinity in the process of fabrication of magnetoresistance sensor, but Co-Ni thin film could be a suitable material for fabrication of magnetoresistance sensor, because of its small affinity and definite magnetoresistance effects.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.5
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• pp.8-14
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• 2007

In this paper, $HfO_2$/Hf stacked film has been applied as the gate dielectric in MOS devices. The $HfO_2$ thin film was deposited on p-type (100) silicon wafers by atomic layer deposition (ALD) using TEMAHf and $O_3$ as precursors. Prior to the deposition of the $HfO_2$ film, a thin Hf metal layer was deposited as an intermediate layer. Round-type MOS capacitors have been fabricated on Si substrates with 2000${\AA}$-thick Al or Pt top electrode. The prepared film showed the stoichiometric components. At the $HfO_2$/Si interface, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. It seems that the intermediate Hf metal layer has a benefit for the enhancement of electric characteristics of gate dielectric in $HfO_2$/Si structure.

• Korean Journal of Materials Research
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• v.9 no.5
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• pp.460-466
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• 1999

The deep level electron traps in AP-MOCVD GaAs/undoped Al\ulcornerGa\ulcornerAs/n-type GaAs heterostructures have been investigated by means of Deep Level Transient Spectroscopy DLTS). In terms of the experimental procedure, GaAs/undoped Al\ulcornerGa\ulcornerAs/n-type GaAs heterostructures were deposited on 2" undoped semi-insulating GaAs wafers by the AP-MOCVD method at $650^{\circ}C$ with TMGa, AsH3, TMAl, and SiH4 gases. The n-type GaAs conduction layers were doped with Si to the target concentration of about 2$\times$10\ulcornercm\ulcorner. The Al content was targeted to x=0.5 and the thicknesses of Al\ulcornerGa\ulcornerAs layers were targeted from 0 to 40 nm. In order to investigate the electrical characteristics, an array of Schottky diodes was built on the heterostructures by the lift-off process and Al thermal evaporation. Among the key results of this experiment, the deep level electron traps at 0.742~0.777 eV and 0.359~0.680 eV were observed in the heterostructures; however, only a 0.787 eV level was detected in n-type GaAs samples without the Al\ulcornerGa\ulcornerAs overlayer. It may be concluded that the 0.787 eV level is an EL2 level and that the 0.742~0.777 eV levels are related to EL2 and residual oxygen impurities which are usually found in MOCVD GaAs and Al\ulcornerGa\ulcornerAs materials grown at $630~660^{\circ}C$. The 0.359~0.680 eV levels may be due to the defects related with the al-O complex and residual Si impurities which are also usually known to exist in the MOCVD materials. Particularly, as the Si doping concentration in the n-type GaAs layer increased, the electron trap concentrations in the heterostructure materials and the magnitude of the C-V hysteresis in the Schottky diodes also increased, indicating that all are intimately related.ated.

• Korean Chemical Engineering Research
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• v.51 no.6
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• pp.666-670
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• 2013

Recovery method of silicon wafer from defective products generated from manufacturing process of silicon solar cells was studied. The removal effect of the N layer and antireflection coating (ARC) of the waste solar cell were investigated at room temperature ($25^{\circ}C$) by variation of concentration of $H_3PO_4$, $NH_4HF_2$, and concentration and types of chelating agent. Removal efficiency was the best in the conditions; 10 wt% $H_3PO_4$ 2.0 wt% $NH_4HF_2$, 1.5 wt% Hydantoin. Increasing the concentration of $H_3PO_4$, the surface contamination degree was increased and the thickness of the silicon wafe became thicker than the thickness before surface treatment because of re-adsorption on the silicon wafer surface by electrostatic attraction of the fine particles changed to (+). The etching method by mixed solution of $H_3PO_4$-$NH_4HF_2$-chelating agents was expected to be great as an alternative to conventional RCA cleaning methods and as the recycle method of waste solar cells, because all processes are performed at room temperature, the process is simple, and less wastewater, the removal efficiency of the surface of the solar cell was excellent.

• Journal of the Korean institute of surface engineering
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• v.38 no.4
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• pp.144-149
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• 2005

ZnO films were produced on the Si(100) and sapphire(0001) wafers by RF magnetron sputtering in terms of processing variables such as substrate temperature and RF power. The stress in films was obtained from the Stoney's formula using a laser scanning device. The stress levels in the films showed the range from $\~40$ MPa to $\~-1100$MPa depending on processing variables. The specimens were thermally cycled from R.T. to $250^{\circ}C$ to investigate the stress variation as a function of temperature. SEM was employed to characterize the microstructure of te films. As the substrate temperature increased, the film surface became rougher and the films showed coarser grains. The optical property o the films was studied by PL measurements. At the highest substrate temperature $800^{\circ}C$ the film exhibited sharper UV peaks unlike other conditions.

• Journal of the Korean Vacuum Society
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• v.21 no.6
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• pp.301-311
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• 2012

Discharge property of plasma jet devices is investigated for the application to the doping processes of crystalline solar cells and others. Current-voltage characteristics are shown as the typical normal-glow discharge in the various gas pressure of plasma jets, such as in the atmospheric plasma jets of Ar-discharge, in the ambient pressure of atmospheric discharge, and in the ambient Ar-pressure of Ar-discharge. The discharge voltage of atmospheric plasma jet is required as low as about 2.5 kV while the operation voltage of low pressure below 200 Torr is low as about 1 kV in the discharge of atmospheric and Ar plasma jets. With a single channel plasma jet, the irradiated plasma current on the doped silicon wafer is obtained high as the range of 10~50 mA. The temperature increasement of wafer is normally about $200^{\circ}C$. In the result of silicon wafers doped by phosphoric acid with irradiating the plasma jets, the doping profiles of phosphorus atoms shows the possibility of plasma jet doping on solar cells.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2005.10a
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• pp.167-170
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• 2005

The two-dimensional (2D) and three-dimensional (3D) diamond-like carbon (DLC) stamps for ultraviolet nanoimprint lithography (UV-NIL) were fabricated using two kinds of methods, which were a DLC coating process followed by the focused ion beam (FIB) lithography and the two-photon polymerization (TPP) patterning followed by nano-scale thick DLC coating. We fabricated 70 nm deep lines with a width of 100 nm and 70 nm deep lines with a width of 150 nm on 100 nm thick DLC layers coated on quartz substrates using the FIB lithography. 200 nm wide lines, 3D rings with a diameter of $1.35\;{\mu}m$ and a height of $1.97\;{\mu}m$, and a 3D cone with a bottom diameter of $2.88\;{\mu}m$ and a height of $1.97\;{\mu}m$ were successfully fabricated using the TPP patterning and DLC coating process. The wafers were successfully printed on an UV-NIL using the DLC stamp. We could see the excellent correlation between the dimensions of features of stamp and the corresponding imprinted features.