• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.629-632
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• 1998

This paper presents a new and simple technique to realize high Q inductor on low resistivity silicon wafer with 6 $\Omega$.cm. This technique is very compatible with bipolar and CMOS standard silicon process. By forming the deep and narrow trenches on the low resistivity wafer substrate under inductor pattern, oxidizing and filling with undoped polysilicon, the low resistivity silicon wafer acts as high resistivity wafer being suitable for the fabrication of high Q inductor. By using this technique the quality factor (Q) for 8-turn spiral inductor was improved up to max. 10.3 at 2 ㎓ with 3.0 $\mu\textrm{m}$ of metal thickness. The experiment results show that Q on low resistivity silicon wafer with the trench technique have been improved more than 2 times compared to the conventional low resistivity silicon wafer without trenches.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.216-216
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• 2012

The purpose of this work is to investigate a back surface field (BSF) on variety wafer resistivity for industrial crystalline silicon solar cells. As pointed out in this manuscript, doping a crucible grown Cz Si ingot with Ga offers a sure way of eliminating the light induced degradation (LID) because the LID defect is composed of B and O complex. However, the low segregation coefficient of Ga in Si causes a much wider resistivity variation along the Ga doped Cz Si ingot. Because of the resistivity variation the Cz Si wafer from different locations has different performance as know. In the light of B doped wafer, we made wider resistivity in Si ingot; we investigated the how resistivities work on the solar cells performance as a BSF quality.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.7
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• pp.1434-1437
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• 2011

Precision measurement of silicon wafer resistivity has been using single-configuration Four-Point Probe(FPP) method. This FPP method have to applying sample size, shape and thickness correction factor for a probe pin spacing to precision measurement of silicon wafer. The deference for resistivity measurement values applied correction factor and not applied correction factor was about 1.0 % deviation. The sample size, shape and thickness correction factor for a probe pin spacing have an effects on precision measurement for resistivity of silicon wafer.

• Journal of the Korean institute of surface engineering
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• v.51 no.3
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• pp.185-190
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• 2018

Dopant-free silicon heterojunction solar cells using Transition Metal Oxide(TMO) such as Molybdenum Oxide($MoO_X$) and Vanadium Oxide($V_2O_X$) have been focused on to increase the work function of TMO in order to maximize the work function difference between TMO and n-Si for a high-efficiency solar cell. One another way to increase the work function difference is to control the silicon wafer resistivity. In this paper, dopant-free silicon heterojunction solar cells were fabricated using the wafer with the various resistivity and analyzed to understand the effect of n-Si work function. As a result, it is shown that the high passivation and junction quality when $V_2O_X$ deposited on the wafer with low work function compared to the high work function wafer, inducing the increase of higher collection probability, especially at long wavelength region. the solar cell efficiency of 15.28% was measured in low work function wafer, which is 34% higher value than the high work function solar cells.

• Electrical & Electronic Materials
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• v.9 no.7
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• pp.727-732
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• 1996

In the present paper, the Cu films 4.mu.m thick were deposited by RF magnetron sputtering method on Si wafer. The Cu films deposited at a condition of 100W, 10mtorr exhibited a low electrical resistivity of 2.3.mu..ohm..cm and densed microstructure, poor adhesion. The Cu films grown by 200W, 20mtorr showed a good adhesion property and higher electrical resistivity of 7.mu..ohm..cm because of porous columnar microstructure. Therefore, The Cu films were deposited by double layer deposition method using RF magnetron sputtering on Si wafer. The dependence of the electrical resistivity, adhesion, and reflectance in the CU films [C $U_{4-d}$(low resistivity) / C $U_{d}$(high adhesion) / Si-wafer] on the thickness of d has been investigated. The films formed with this deposition methods had the low electrical resistivity of about 2.6.mu..ohm..cm and high adhesion of about 700g/cm.m.m.

• Korean Journal of Materials Research
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• v.23 no.6
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• pp.316-321
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• 2013

The electrical properties and surface morphology changes of a silicon wafer as a function of the HF concentration as the wafer is etched were studied. The HF concentrations were 28, 30, 32, 34, and 36 wt%. The surface morphology changes of the silicon wafer were measured by an SEM ($80^{\circ}$ tilted at ${\times}200$) and the resistivity was measured by assessing the surface resistance using a four-point probe method. The etching rate increased as the HF concentration increased. The maximum etching rate 27.31 ${\mu}m/min$ was achieved at an HF concentration of 36 wt%. A concave wave formed on the wafer after the wet etching process. The size of the wave was largest and the resistivity reached 7.54 $ohm{\cdot}cm$ at an 30 wt% of HF concentration. At an HF concentration of 30 wt%, therefore, a silicon wafer should have good joining strength with a metal backing as well as good electrical properties.

• Korean Journal of Materials Research
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• v.23 no.6
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• pp.322-328
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• 2013

The relationship the between electrical properties and surface roughness (Ra) of a wet-etched silicon wafer were studied. Ra was measured by an alpha-step process and atomic force microscopy (AFM) while varying the measuring range $10{\times}10$, $40{\times}40$, and $1000{\times}1000{\mu}m$. The resistivity was measured by assessing the surface resistance using a four-point probe method. The relationship between the resistivity and Ra was explained in terms of the surface roughness. The minimum error value between the experimental and theoretical resistivities was 4.23% when the Ra was in a range of $10{\times}10{\mu}m$ according to AFM measurement. The maximum error value was 14.09% when the Ra was in a range of $40{\times}40{\mu}m$ according to AFM measurement. Thus, the resistivity could be estimated when the Ra was in a narrow range.

• Korean Journal of Materials Research
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• v.25 no.1
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• pp.16-20
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• 2015

In this study, in order to improve the efficiency of n-type monocrystalline solar cells with an Alu-cell structure, we investigate the effect of the amount of Al paste in thin n-type monocrystalline wafers with thicknesses of $120{\mu}m$, $130{\mu}m$, $140{\mu}m$. Formation of the Al doped $p^+$ layer and wafer bowing occurred from the formation process of the Al back electrode was analyzed. Changing the amount of Al paste increased the thickness of the Al doped $p^+$ layer, and sheet resistivity decreased; however, wafer bowing increased due to the thermal expansion coefficient between the Al paste and the c-Si wafer. With the application of $5.34mg/cm^2$ of Al paste, wafer bowing in a thickness of $140{\mu}m$ reached a maximum of 2.9 mm and wafer bowing in a thickness of $120{\mu}m$ reached a maximum of 4 mm. The study's results suggest that when considering uniformity and thickness of an Al doped $p^+$ layer, sheet resistivity, and wafer bowing, the appropriate amount of Al paste for formation of the Al back electrode is $4.72mg/cm^2$ in a wafer with a thickness of $120{\mu}m$.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1648-1650
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• 1996

In present paper, Cu films $4{\mu}m$, thick were fabricated by dual deposition methods using RF magnetron sputtering on Si wafer. The dependence of the electrical resistivity, adherence, and reflection in Cu films [$Cu_{4-x}$(low resistivity) / $Cu_x$(high adherence) / Si- wafer] on the x thickness have been investigated. Cu films of $4{\mu}m$ thickness formed with dual deposition methods had the low electrical resistivity of about $2.6{\mu}{\Omega}{\cdot}cm$ and high adherence of about 700g/cm. In conclusion, it is possible for these films to be used for micro-devices.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1361-1363
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• 1998

Poly-Si grain boundaries act as potential barriers as well as recombination centers for the photo-generated carriers in solar cells. Thereby, grain boundaries of poly-Si are considered as a major source of the poly-Si cell efficiency was reduced This paper investigated grain boundary effect of poly-Si wafer prior to the solar cell fabrication. By comparing I-V characteristics inner grain, on and across the grain boundary, we were able to detect grain potentials. To reduce grain boundary effect we carried out pretreatment, $POCl_3$ gettering, and examined carrier lifetime. This paper focuses on resistivity variation effect due to grain boundary of poly-Si. The resistivity of the inner grain was $2.2{\Omega}-cm$, on the grain boundary$2.3{\Omega}-cm$, across the grain boundary $2.6{\Omega}-cm$. A measured resistivity varied depending on how many grains were included inside the four point probes. The resistivity increased as the number of grain boundaries increased. Our result can contribute to achieve high conversion efficiency of poly-Si solar cell by overcoming the grain boundary influence.