• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.22-25
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• 2005

In this research, a wafar-level transfer method of cantilever array on a conventional CMOS circuit has been developed for high density probe-based data storage. The transferred cantilevers were silicon nitride ($Si_3N_4$) cantilevers integrated with poly silicon heaters and piezoelectric sensors, called thermo-piezoelectric $Si_3N_4$ cantilevers. In this process, we did not use a SOI wafer but a conventional p-type wafer for the fabrication of the thermo-piezoelectric $Si_3N_4$ cantilever arrays. Furthermore, we have developed a very simple transfer process, requiring only one step of cantilever transfer process for the integration of the CMOS wafer and cantilevers. Using this process, we have fabricated a single thermo-piezoelectric $Si_3N_4$ cantilever, and recorded 65nm data bits on a PMMA film and confirmed a charge signal at 5nm of cantilever deflection. And we have successfully applied this method to transfer 34 by 34 thermo-piezoelectric $Si_3N_4$ cantilever arrays on a CMOS wafer. We obtained reading signals from one of the cantilevers.

• Transactions of the Society of Information Storage Systems
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• v.2 no.2
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• pp.96-99
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• 2006

In this research, a wafer-level transfer method of cantilever away on a conventional CMOS circuit has been developed for high density probe-based data storage. The transferred cantilevers were silicon nitride ($Si_3N_4$) cantilevers integrated with poly silicon heaters and piezoelectric sensors, called thermo-piezoelectric $Si_3N_4$ cantilevers. In this process, we did not use a SOI wafer but a conventional p-type wafer for the fabrication of the thermo-piezoelectric $Si_3N_4$ cantilever arrays. Furthermore, we have developed a very simple transfer process, requiring only one step of cantilever transfer process for the integration of the CMOS wafer and cantilevers. Using this process, we have fabricated a single thermo-piezoelectric $Si_3N_4$ cantilever, and recorded 65nm data bits on a PMMA film and confirmed a charge signal at 5nm of cantilever deflection. And we have successfully applied this method to transfer 34 by 34 thermo-piezoelectric $Si_3N_4$ cantilever arrays on a CMOS wafer. We obtained reading signals from one of the cantilevers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.1029-1034
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• 2012

This paper presents a cost-effective and high-performance film bulk acoustic resonator (FBAR) duplexer module for US-PCS handset applications. The FBAR device uses a glass wafer level packaging process, which is a more cost-effective alternative to the typical silicon capping process. The maximum insertion losses of the FBAR duplexer at the Tx and Rx bands are of 1.9 and 2.4 dB, respectively. The total thickness of the duplexer module is 1.2 mm, including the glass-wafer bonded Tx/Rx FBAR devices, PCB board, and transfer molding material.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.11.1-11.1
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• 2011

We have developed a simple synthetic method for fabricating a wafer-scale colloidal crystal film of 2D crystals in a 1D stack based on a combination of two simple processes : the self-assembly of polystyrene (PS) nanospheres at the water-air interface and the layer-by-layer (LbL) scooping transfer technique. The main advantage of this approach is that it allows excellent control of the thickness (at a layer level) of the crystals and the formation of a vertical crack-free layer over a wafer-scale (4 inch). We investigate the optical and morphological properties of the PhC multilayers fabricated using various mono-sized colloidal crystals (250, 300, 350, 420, 580, 720, and 850 nm), and mixed binary colloidal crystals (300/350 and 250/350 nm).

• Journal of Korean Society of Industrial and Systems Engineering
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• v.38 no.4
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• pp.159-167
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• 2015

We consider a wafer lot transfer/release planning problem from semiconductor wafer fabrication facilities to probing facilities with the objective of minimizing the deviation of workload and total tardiness of customers' orders. Due to the complexity of the considered problem, we propose a two-level hierarchical production planning method for the lot transfer problem between two parallel facilities to obtain an executable production plan and schedule. In the higher level, the solution for the reduced mathematical model with Lagrangian relaxation method can be regarded as a coarse good lot transfer/release plan with daily time bucket, and discrete-event simulation is performed to obtain detailed lot processing schedules at the machines with a priority-rule-based scheduling method and the lot transfer/release plan is evaluated in the lower level. To evaluate the performance of the suggested planning method, we provide computational tests on the problems obtained from a set of real data and additional test scenarios in which the several levels of variations are added in the customers' demands. Results of computational tests showed that the proposed lot transfer/planning architecture generates executable plans within acceptable computational time in the real factories and the total tardiness of orders can be reduced more effectively by using more sophisticated lot transfer methods, such as considering the due date and ready times of lots associated the same order with the mathematical formulation. The proposed method may be implemented for the problem of job assignment in back-end process such as the assignment of chips to be tested from assembly facilities to final test facilities. Also, the proposed method can be improved by considering the sequence dependent setup in the probing facilities.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2002.05a
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• pp.285-292
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• 2002

A cluster tool for semiconductor manufacturing is an integrated device that consists of several single wafer processing modules and a wafer transport module based on a robot. The distributed module controllers are integrated by an inter-module communication network and coordinated by a centralized controller, called a cluster tool controller (CTC). Since the CTC monitors and coordinates the distributed complex module controllers for advanced process control, complex commuication messaging and services between the CTC and the module controllers are required. A SEMI standard, CTMC(Cluster Tool Module Communication), specifies application-level communication service requirements for inter-module communication. We propose the use of high-level fieldbuses, for instance. PROFIBUS-FMS, for implementing CTMC since the high-level fieldbuses are well suited for complex real-time distributed manufacturing control applications. We present a way of implementing CTMC using PROFIBUS-FMS as the communication enabler. We first propose improvements of a key object of CTMC for material transfer and the part transfer protocol to meet the functional requirements of modem advanced cluster tools. We also discuss mapping objects and services of CTMC to PROFIBUS-FMS communication objects and services. Finally, we explain how to implement the mappings.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.05a
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• pp.157-162
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• 2005

The wafer's size has been increased up to 300mm according as the devices have been integrated sophisticatedly. For this process to make 300mm-wafer, it is required strict level which removes the particulates on the surface of wafer. Therefore we need new type wet-station which can reduce DI water and chemical in the cleaning process. Moreover, it is very important to control the temperature and the concentration of chemical wet-stat ion. The chemical supply system which is used currently is not only difficult to make a fit mixing rate of chemical in cleaning process, but also it is difficult to make fit quantity and temperature. We propose new chemical supply system, which overcomes the problems via analysis of fluid and thermal transfer on chemical supply system,

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.6
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• pp.271-277
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• 2002

In this paper, a MEMS silicon package is newly designed, fabricated for HMIC, and characterized for microwave and millimeter-wave device applications. The proposed package is fabricated by using two high resistivity silicon substrates and surface/bulk micromachining technology. It has a good performance characteristic such as -20㏈ of $S_11$/ and -0.3㏈ of $S_21$ up to 20㎓, which is useful in microwave region. It has also better heat transfer characteristics than the commonly used ceramic package. Since the proposed silicon MEMS package is easy to fabricate and wafer level chip scale packaging is also possible, the production cost can be much lower than the ceramic package. Since it will be a promising low-cost package for mobile/wireless applications.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.9-9
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• 2011

The transfer of nano-science accomplishments into technology is severely hindered by a lack of understanding of barriers to nanoscale manufacturing. The NSF Center for High-rate Nanomanufacturing (CHN) is developing tools and processes to conduct fast massive directed assembly of nanoscale elements by controlling the forces required to assemble, detach, and transfer nanoelements at high rates and over large areas. The center has developed templates with nanofeatures to direct the assembly of carbon nanotubes and nanoparticles (down to 10 nm) into nanoscale trenches in a short time (in seconds) and over a large area (measured in inches). The center has demonstrated that nanotemplates can be used to pattern conducting polymers and that the patterned polymer can be transferred onto a second polymer substrate. Recently, a fast and highly scalable process for fabricating interconnects from CMOS and other types of interconnects has been developed using metallic nanoparticles. The particles are precisely assembled into the vias from the suspension and then fused in a room temperature process creating nanoscale interconnect. The center has many applications where the technology has been demonstrated. For example, the nonvolatile memory switches using (SWNTs) or molecules assembled on a wafer level. A new biosensor chip (0.02 $mm^2$) capable of detecting multiple biomarkers simultaneously and can be in vitro and in vivo with a detection limit that's 200 times lower than current technology. The center has developed the fundamental science and engineering platform necessary to manufacture a wide array of applications ranging from electronics, energy, and materials to biotechnology.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.11B no.3
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• pp.112-118
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• 2001

In the near future, the voltage of power system for passenger vehicle will be changed to 42V from existing 14V./ Because of increasing power and voltage ratings used in the vehicle the motor drive system has high switching dv/dt and it generates electromagnetic interference (EMI) To solve these problems multi-level inverter system may be used The feature of multi-level inverter is the output voltage to be synthesized from several levels of voltage Because of this feature high switching dv/dt and EMI can be reduced in the multi-level inverter system But as the number of level is increased manufacturing cost is getting expensive and system size is getting large. Because of these disadvantages the application of multi-level inverter has been restricted only to high power drives. The method to reduce manufacturing cost and system size is to integrate circuit of multi-level inverter into a few chips But isolated power supply and signal isolation circuit using transformer or opto-coupler for drive circuit are obstacles to implement the integrated circuit (IC) In this paper a drive circuit of 4-level inverter suitable for integration to hybrid or one chip is proposed In the proposed drive circuit DC link voltage is used directly as the power source of each gate drive circuit NPN transistors and PNP transistors are used to isolate to transfer the control signals. So the proposed drive circuit needs no transformers and opto-couplers for electrical isolation of drive circuit and is constructed only using components to be implemented on a silicon wafer With th e proposed drive circuit 4- level inverter system will be possible to be implemented through integrated circuit technology Using the proposed drive circuit 4- level inverter system is constructed and the validity and characteristics of the proposed drive circuit are proved through the experiments.