• Industrial Engineering and Management Systems
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• v.2 no.1
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• pp.9-27
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• 2003

In a wafer fabrication factory, the completion time of an order is affected by many factors related to the specifics of the order and the status of the system, so is difficult to predict precisely. The level of influence of each factor on the order completion time may also depend on the production system characteristics, such as the rules for releasing and dispatching. This paper presents a method to identify those factors that significantly impact upon the order completion time under various combinations of scheduling rules. Computer simulations and statistical analyses were used to develop effective due date assignment models for improving the due date related performances. The first step of this research was to select the releasing and dispatching rules from those that were cited so frequently in related wafer fabrication factory researches. Simulation and statistical analyses were combined to identify the critical factors for predicting order completion time under various combinations of scheduling rules. In each combination of scheduling rules, two efficient due date assignment models were established by using the regression method for accurately predicting the order due date. Two due date assignment models, called the significant factor prediction model (SFM) and the key factor prediction model (KFM), are proposed to empirically compare the due date assignment rules widely used in practice. The simulation results indicate that SFM and KFM are superior to the other due date assignment rules. The releasing rule, dispatching rule and due date assignment rule have significant impacts on the due date related performances, with larger improvements coming from due date assignment and dispatching rules than from releasing rules.

• Journal of Korean Institute of Industrial Engineers
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• v.35 no.4
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• pp.266-279
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• 2009

This paper focuses on the problem of scheduling wafer lots with limited waiting times between pairs of consecutive operations in a semiconductor wafer fabrication facility. For the problem of minimizing total tardiness of orders, we develop a priority rule based scheduling method in which a scheduling decision for an operation is made based on the states of workstations for the operation and its successor or predecessor operation. To evaluate performance of the suggested scheduling method, we perform simulation experiments using real factory data as well as randomly generated data sets. Results of the simulation experiments show that the suggested method performs better than a method suggested in other research and the one that has been used in practice.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1995.04a
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• pp.939-954
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• 1995

We propose a policy for controlling the release of raw wafers into the semiconductor wafer fabrication lines. The proposed policy exploits up-to-date factory floor information gathered by tracking systems used to calculate the time and amount of a new release to minimize mean flow times and mean tardiness while maintaining the maximum output rates of the system. Extensive computer experiments show that the proposed policy results in significant improvements for the same output rates compared to existing release rules.

• Journal of Mechanical Science and Technology
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• v.20 no.12
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• pp.2025-2033
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• 2006

This paper presents, the design of a latch mechanism for wafer containers in a standard mechanical interface environment. For an integrated circuits fabrication factory, the standard mechanical interfaced wafer container is an effective tool to prevent wafers from particle contamination during wafer storage, transporting or transferring. The latch mechanism inside the container door is used to latch and further seal the wafer container for safety and air quality. Kinematic characteristics of the mechanism are established by analyzing the required functions of the mechanisms. Based on these characteristics, a methodology for enumerating feasible latch mechanisms is developed. New mechanisms with one degree-of-freedom and up to five links are generated. An optimum design is also identified with respect to the criteria pertinent to the application. The computer-aided simulation is also built to verify the design.

• Industrial Engineering and Management Systems
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• v.4 no.1
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• pp.47-53
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• 2005

The efficiency of fabrication (fab) operation is one of the key factors in order for a semiconductor manufacturing company to stay competitive. Optimization of manpower and forecasting manpower needs in a modern fab is an essential part of the future strategic planing and a very important to the operational efficiency. As the semiconductor manufacturing technology has entered the 8-inch wafer era, the complexity of fab operation increases with the increase of wafer size. The wafer handling method has evolved from manual mode in 6-inch wafer fab to semi-automated or fully automated factory in 8-inch and 12-inch wafer fab. The distribution of manpower requirement in each specialty varied as the trend of fab operation goes for downsizing manpower with automation and outsourcing maintenance work. This paper is to study the specialty distribution of manpower from the requirement in a typical 6-inch, 8-inch to 12-inch wafer fab. The human resource planning in today’s fab operation shall consider many factors, which include the stability of technical talents. This empirical study mainly focuses on the human resource planning, the manpower distribution of specialty structure and the forecast model of internal demand/supply in current semiconductor manufacturing company. Considering the market fluctuation with the demand of varied products and the advance in process technology, the study is to design a headcount forecast model based on current manpower planning for direct labour (DL) and indirect labour (IDL) in Taiwan’s fab. The model can be used to forecast the future manpower requirement on each specialty for the strategic planning of human resource to serve the development of the industry.

• Safety and Health at Work
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• v.2 no.3
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• pp.210-217
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• 2011

Objectives: The purpose of this study was to measure the concentration of volatile organic compound (VOC)s originated from the chemicals used and/or derived from the original parental chemicals in the photolithography processes of semiconductor manufacturing factories. Methods: A total of four photolithography processes in 4 Fabs at three different semiconductor manufacturing factories in Korea were selected for this study. This study investigated the types of chemicals used and generated during the photolithography process of each Fab, and the concentration levels of VOCs for each Fab. Results: A variety of organic compounds such as ketone, alcohol, and acetate compounds as well as aromatic compounds were used as solvents and developing agents in the processes. Also, the generation of by-products, such as toluene and phenol, was identified through a thermal decomposition experiment performed on a photoresist. The VOC concentration levels in the processes were lower than 5% of the threshold limit value (TLV)s. However, the air contaminated with chemical substances generated during the processes was re-circulated through the ventilation system, thereby affecting the airborne VOC concentrations in the photolithography processes. Conclusion: Tens of organic compounds were being used in the photolithography processes, though the types of chemical used varied with the factory. Also, by-products, such as aromatic compounds, could be generated during photoresist patterning by exposure to light. Although the airborne VOC concentrations resulting from the processes were lower than 5% of the TLVs, employees still could be exposed directly or indirectly to various types of VOCs.