• Journal of the Semiconductor & Display Technology
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• v.13 no.3
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• pp.61-67
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• 2014

Micro-cracks in crystalline silicon wafer often result in wafer breakage in solar wafer manufacturing, and also their existence may lead to electrical failure in post fabrication inspection. Therefore, the reliable detection of micro-cracks is of importance in the photovoltaic industry. In this paper, an experimental method to select optimal parameters in anisotropic diffusion filter is proposed. It can reliably detect micro-cracks by the distinct extension of boundary as well as noise reduction in near-infrared image patterns of micro-cracks. Its performance is verified by experiments of several type cracks machined.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.5
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• pp.350-355
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• 2000

The fabrication of sapphire wafer in C plane has been developed by horizontal Bridgeman method and GaN based semiconductor epitaxial growth has been carried out in metal organic chemical vapour deposition. The single crystalline ingot of sapphire has been utilized for 2 inch sapphire wafers and wafer slicing and lapping machines were designed. These several steps of lapping processes provided the mirror-like surface of sapphire wafer. The measurements of the surface flatness and the roughness were carried out by the atomic force microscope. The GaN thin film growth on the developed wafer was confirmed the wafer quality and applicability to blue light emitting devices.

• Korean Journal of Computational Design and Engineering
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• v.19 no.3
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• pp.214-223
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• 2014

This paper presents a bottleneck detection framework using simulation approach in a wafer FAB (Fabrication). In a semiconductor manufacturing industry, wafer FAB facility contains various equipment and dozens kinds of wafer products. The wafer FAB has many characteristics, such as re-entrant processing flow, batch tools. The performance of a complex manufacturing system (i.e. semiconductor wafer FAB) is mainly decided by a bottleneck. This paper defines the problem of a bottleneck process and propose a simulation based framework for bottleneck detection. The bottleneck is not the viewpoint of a machine, but the viewpoint of a step with the highest WIP in its upstream buffer and severe fluctuation. In this paper, focus on the classification of bottleneck steps and then verify the steps are not in a starvation state in last, regardless of dispatching rules. By the proposed framework of this paper, the performance of a wafer FAB is improved in on-time delivery and the mean of minimum of cycle time.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.29-33
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• 2012

The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

• Proceedings of the Materials Research Society of Korea Conference
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• 1997.10a
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• pp.170-170
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• 1997

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1108-1109
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• 2008

To survive in outdoor environments, photovoltaic modules rely on packaging materials to provide requisite durability. We analyzed the properties of encapsulant materials that are important for photovoltaic module packaging. Recently, the thickness of solar cell gets thinner to reduce the quantity of silicon. And the reduced thickness make it easy to be broken while PV module fabrication process. Solar cell's micro cracks are increasing the breakage risk over the whole value chain from the wafer to the finished module, because the wafer or cell is exposed to tensile stress during handling and processing. This phenomenon might make PV module's maximum power and durability down. So, when using thin solar cell for PV module fabrication, it is needed to optimize the material and fabrication condition which is quite different from normal thick solar cell process. Normally, gel-content of EVA sheet should be higher than 80% so PV module has long term durability. But high gel-content characteristic might cause micro-crack on solar cell. In this experiment, we fabricated several specimen by varying curing temperature and time condition. And from the gel-content measurement, we figure the best fabrication condition. Also we examine the crack generation phenomenon during experiment.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.372.2-372.2
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• 2016

Various nanobiosensors have been developed and extensively investigated. For their practical applications, however, the reproducibility and uniformity should be good enough and the mass-production should be possible. To fabricate anodized aluminium oxide (AAO)-based nanobiosesnor on wafer scale, we have designed and constructed a wafer-scale anodizing system. $1{\mu}m$-thick-aluminum is deposited on 4 inch SiO2/Si substrate and then anodized, resulting in uniform nanopores with an average pore diameter of about 65 nm. Furthermore, most AAO sensors constructed on this wafer provide capacitance values of 30 nF ~ 60 nF in PBS, demonstrating their uniformity.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.3
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• pp.120-125
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• 2002

Si-wafers for solar cells were cast in a size of $50{\times}46{\times}0.5{\textrm}{mm}^3$ by vacuum casting method. The graphite mold coated by BN powder, which was to prevent the reaction of carbon with the molten silicon, was used. Without coating, the wetting and reaction of Si melt to graphite mold was very severe. In the case of BN coating, SiC was formed in the shape of tiny islands at the surface of Si wafer by the reaction between Si-melt and carbon of the graphite mold on the high temperature. The grain size was about 1 mm. The efficiency of Si solar cell was lower than that of Si solar cell fabricated on commercial single and poly crystalline Si wafer. The reason of low efficiency was discussed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1224-1231
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• 2003

This paper reports on the air-gap type thin film bulk acoustic wave resonator(FBAR) using ultra thin wafer with thickness of 50$\mu\textrm{m}$. It was fabricated to realize a small size devices and integrated objects using MEMS technology for flexible microsystems. To reduce a error of experiment, MATLAB simulation was executed using material characteristic coefficient. Fabricated thin FBAR consisted of piezoelectric film sandwiched between metal electrodes. Used piezoelectric film was the aluminum nitride(AlN) and electrode was the molybdenum(Mo). Thin wafer was fabricated by wet etching and dry etching, and then handling wafer was used to prevent damage of FBAR. The series resonance frequency and the parallel frequency measured were 2.447㎓ and 2.487㎓, respectively. Active area is 100${\times}$100$\mu\textrm{m}$$^2$.Q-factor was 996.68 and K$^2$$\_$eff/ was 3.91％.

• The Korean Journal of Ceramics
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• v.3 no.1
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• pp.18-20
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• 1997

The fabrication process of silicon-diamond(SOD) structure wafer were studied. Microwave plasma chemical vapor deposition (MWPCVD) and annealing technology were used to synthesize diamond film with high resistivity and thermal conductivity. Bonding and etchback silicon-on-diamond (BESOD) were utilized to form supporting substrate and single silicon thin layer of SOD wafer. At last, a SOD structure wafer with 0.3~1$\mu\textrm{m}$ silicon film and 2$\mu\textrm{m}$ diamond film was prepared. The characteristics of radiation for a CMOS integrated circuit (IC) fabricated by SOD wafer were studied.