• Title/Summary/Keyword: voltage-controlled oscillator

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Low Phase Noise Series-coupled VCO using Current-reuse and Armstrong Topologies

  • Ryu, Hyuk;Ha, Keum-Won;Sung, Eun-Taek;Baek, Donghyun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.1
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    • pp.42-47
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    • 2017
  • This paper proposes a new series-coupled voltage-controlled oscillator (VCO). The proposed VCO consists of four current-reuse Armstrong VCOs (CRA-VCOs) coupled by four transformers. The series-coupling, current-reuse, and Armstrong topologies improve the phase noise performance by increasing the negative-Gm of the VCO core with half the current consumption of a conventional differential VCO. The proposed VCO consumes 6.54 mW at 9.78 GHz from a 1-V supply voltage. The measured phase noise is -115.1 dBc/Hz at an offset frequency of 1 MHz, and the FoM is -186.5 dBc/Hz. The frequency tuning range is from 9.38-10.52 GHz. The core area is $0.49mm^2$ in a $0.13-{\mu}m$ CMOS process.

Design and fabrication of the 2.4 to 2.5 GHz voltage controlled oscillator using microstrip patch antenna (마이크로스트립 패치 안테나를 이용한 2.4 ~ 2.5GHz 에서 동작하는 전압 조정 발진기의 설계 및 제작)

  • 황재호;명노훈
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.2
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    • pp.78-86
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    • 1996
  • Solid-state devices can be directly integrated with a planar antenna to form active antenna elements. In this paper, the voltage controlled oscillator (VCO) is designed and fabricated at 2.4 to 2.5 GHz using a microstrip patch antenna. A varactor diode is used as avariable reactance. The predicted frequency tuning range of the VCO is 2.448 to 2.498 GHz in the design procedure and the fabricated VCO has 2.446 to 2.498 GHz frequency tuning range when the varactor tuning voltage is varied from 0 to 11V. Transmitted power output of the patch antenna which serves both as a rsonator and a radiating element for VCO is about 18 mW over this tuning range.

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Quadrature VCO as a Subharmonic Mixer

  • Oh, Nam-Jin
    • International journal of advanced smart convergence
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    • v.10 no.3
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    • pp.81-88
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    • 2021
  • This paper proposes two types of subharmonic RF receiver front-end (called LMV) where, in a single stage, quadrature voltage-controlled oscillator (QVCO) is stacked on top of a low noise amplifier. Since the QVCO itself plays the role of the single-balanced subharmonic mixer with the dc current reuse technique by stacking, the proposed topology can remove the RF mixer component in the RF front-end and thus reduce the chip size and the power consumption. Another advantage of the proposed topologies is that many challenges of the direct conversion receiver can be easily evaded with the subharmonic mixing in the QVCO itself. The intermediate frequency signal can be directly extracted at the center taps of the two inductors of the QVCO. Using a 65 nm complementary metal oxide semiconductor (CMOS) technology, the proposed subharmonic RF front-ends are designed. Oscillating at around 2.4 GHz band, the proposed subharmonic LMVs are compared in terms of phase noise, voltage conversion gain and double sideband noise figure. The subharmonic LMVs consume about 330 ㎼ dc power from a 1-V supply.

The Impact of Gate Leakage Current on PLL in 65 nm Technology: Analysis and Optimization

  • Li, Jing;Ning, Ning;Du, Ling;Yu, Qi;Liu, Yang
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.1
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    • pp.99-106
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    • 2012
  • For CMOS technology of 65 nm and beyond, the gate leakage current can not be negligible anymore. In this paper, the impact of the gate leakage current in ring voltage-controlled oscillator (VCO) on phase-locked loop (PLL) is analyzed and modeled. A voltage -to-voltage (V-to-V) circuit is proposed to reduce the voltage ripple on $V_{ctrl}$ induced by the gate leakage current. The side effects induced by the V-to-V circuit are described and optimized either. The PLL design is based on a standard 65 nm CMOS technology with a 1.8 V power supply. Simulation results show that 97 % ripple voltage is smoothed at 216 MHz output frequency. The RMS and peak-to-peak jitter are 3 ps and 14.8 ps, respectively.

Phase Locked VCDRO for the 20 GHz Point-to-point Radio Link (20 GHz 고정국용 위상고정 VCDRO)

  • 주한기;장동필
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.10 no.6
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    • pp.816-824
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    • 1999
  • Design and performance of 18 GHz phase locked dielectric resonator oscillator(PLDRO) for Point-to-point radio link using analog phase locked loop is described which achieve high stability and low SSB phase noise. The module consists of an 18 GHz voltage controlled dielectric resonator oscillator(VCDRO), buffered amplifier, analog phase detector which are integrated to form a miniature hybrid circuit. In addition, containing a low phase noise VHF PLL has been designed to lock any other conventional N times frequency of crystal oscillator. The module achieves stable phase locked state, exhibits output power of 21 dBm at 18.00 GHz, -34 dBc harmonic suppression and -75 dBc/Hz phase noise at 10 kHz offset frequency from carrier.

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Design of The Bluetooth Negative Resistor Oscillator using the Improved Spiral Inductor (향상된 나선형 인덕터를 이용한 블루투스 부성저항발진기 설계)

  • 손주호;최석우;김동용
    • Journal of Korea Multimedia Society
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    • v.6 no.2
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    • pp.325-331
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    • 2003
  • In this paper, we designed a spiral inductor and voltage controlled oscillator with the negative resistor for the bluetooth receiver by using 0.25$\mu\textrm{m}$ 1-poly 5-metal CMOS n-well process. The proposed inductor, which applies multi layer metal structure, is a structure that decreases resistance value by increasing he metal thickness. As the resistance value decreases, the quality factor Q has improved. Also, voltage-controlled oscillator is designed applying 1 port negative resistance, and changes its oscillating frequency by varying outside capacitor values. The simulation results show that oscillating frequency is 2.33~2.58GHz changing from 2pF to 14pF, and the oscillator has oscillating power over 0dBm.

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A Design of the Voltage-Controlled Oscillator for Wireless Subscriber Network (무선가입자회선망용 전압제어발진기 설계)

  • Hur, Chang-Wu;Choi, Jun-Su
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.12
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    • pp.2205-2209
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    • 2007
  • In this paper, a voltage controlled oscillator(VCO) of core components for wireless subscriber network is designed. The type of oscillator is colpits method and the oscillator device uses a LC resonator. The product is made on FR-4 substrate with dielectric constant of 4.6. The designed VCO is operated at 3.2V, 10mA and has output value of 0.67dB. The VCO's phase noise property is -102DBc/Hz at offset frequence of 100kHz. The fabricated VCO is the same as target value and can be used for wireless subscriber network.

Design of Voltage Controlled Oscillator Using the BiCMOS (BiCMOS를 사용한 전압 제어 발진기의 설계)

  • Lee, Yong-Hui;Ryu, Gi-Han;Yi, Cheon-Hee
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.11
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    • pp.83-91
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    • 1990
  • VOC(coltage controlled oscillator) circuits are necessary in applications such at the demodul-ation of FM signals, frequency synthesizer, and for clock recovery from digital data. In this paper, we designed the VCO circuit based on a OTA(operational transconductance amplifier) and the OP amp which using a differential amplifier by BiCMOS circuit. It consists of a OTA, voltage contorolled integrator and a schmitt trigger. Conventional VCO circuits are designed using the CMOS circuit, but in this paper we designed newly BiCMOS VCO circuit which has a good drive avlity, As a result of SPICE simulation, output frequency is 141KHz at 105KHz, and sensitivity is 15KHz.

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A Design of Push-push Voltage Controlled Oscillator using Frequency Tuning Circuit with Single Transmission Line (단일 전송선로의 주파수 동조회로를 이용한 push-push 전압제어 발진기의 설계 및 제작)

  • Ryu, Keun-Kwan;Kim, Sung-Chan
    • Journal of IKEEE
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    • v.16 no.2
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    • pp.121-126
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    • 2012
  • In this paper, a push-push VCDRO (Voltage Controlled Dielectric Resonator Oscillator) with a modified frequency tuning structure is investigated. The push-push VCDRO designed at 16GHz is manufactured using a LTCC (Low Temperature Co-fired Ceramic) technology to reduce the circuit size. The frequency tuning structure is embedded in intermediate layer of A6 substrate by an advantage of LTCC process. Experimental results show that the fundamental frequency suppression is above 30dBc, the frequency tuning range is 0.43MHz over control voltage of 0 to 12V, and phase noise of push-push VCDRO presents a good performance of -103dBc/Hz at 100KHz offset frequency from carrier.

Design of the Voltage Controlled Oscillator for Low Voltage (저전압용 전압제어발진기의 설계)

  • Lee, Jong-In;Jung, Dong-Soo;Jung, Hak-Kee;Yoon, Young-Nam;Lee, Sang-Young
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.11
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    • pp.2480-2486
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    • 2012
  • The design of low voltage LC-VCO(LC Voltage Controlled Oscillator) has been presented to optimize the phase noise and power consumption for the block of frequency synthesis to satisfy WCDMA system specification in this paper. The parameters for minimum phase noise has been obtained in the region of design, using the lines of the tuning range and the excess gain in the plane of the inductance and the transconductance of MOS transistor to compensate the loss of LC-tank. As a result of simulation, the phase noise characteristics is -113dBc/Hz for offset of 1MHz. The optimum designed LC-VCO has been fabricated using the process of 0.25um CMOS. As a result of measurement for fabricated chip, the phase noise characteristics is -116dBc/Hz for offset of 1MHz. The power consumption is 15mW, and Kvco is 370MHz/V.