• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.4
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• pp.51-58
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• 1985

A simple model for the impurity profile in an ion-implanted channel layer of an enhance-ment type IGFET is assumed and a simple expression for the threshold voltage is derived by the assumed impurity profile. In application, the concept of correction factor K is used and the value of threshold voltage is well agreed with experimental value. Also, 1-V character-istics curve is well agreed with experimental value. In addition, this program is packaged and is utilized.

• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.347-349
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• 2016

본 논문에서는 dopant density에 의존적인 pn junction의 breakdown 특성을 향상시키기 위하여, doping density와 doping profile에 대하여 분석했다. Doping density와 doping profile은 역방향 junction breakdown voltage를 결정하는 중요한 요소인 공핍영역의 두께와 공핍영역 내에 인가되는 electric field를 결정한다. Uniform doping profile과 Gaussian doping profile을 비교했고, 고전압 환경에서 사용할 수 있는 소자를 제작하는데 더욱 적절한 doping profile과 doping 농도에 대해 기술했다.

• Journal of Electrical Engineering and Technology
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• v.4 no.3
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• pp.310-314
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• 2009

This paper presents the improvement of the voltage profiles of power system networks by the inclusion of Unified Power Flow Controller (UPFC). The mathematical model of the UPFC is incorporated in the load flow algorithm and the L-index is calculated for the different values of the control parameter r $and{\gamma}$. The positioning of the UPFC device is changed to minimize the sum of the squares of the L-indices at all load buses. The test cases considered for the improvement of voltage profile with the WSCC 9-bus and IEEE 30 bus system. With the best position of UPFC along with the control parameters the improvement in voltage profile of the power system networks are obtained. The results obtained are quite encouraging compared with other techniques used to identify the best location of UPFC.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.10
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• pp.641-645
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• 2017

In this study, an epoxy insulation barrier for high voltage GIS was developed using epoxy and a filler with a Young's modulus of 11 GPa. The material was investigated using a simulation of the principal stress, displacement, and safety factors while optimizing the profile shape. The simulation showed that thelarger Young's modulus of the $Al_2O_3$ filler compared to the $SiO_2$ in the epoxy insulation can contribute to an increase in resistance to mechanical fracturing for theoptimized profile barrier in high voltage GIS. In addition, the safety factor was improved by 10%. It can be concluded that the mechanical fracturing properties of the insulation barrier can be enhanced by increasing the content of the elastic filler, $Al_2O_3$, for high voltage GIS applications.

• Journal of Electrical Engineering and Technology
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• v.8 no.6
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• pp.1261-1268
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• 2013

This study proposes a voltage and reactive coordinative control strategy with distributed generator (DG) in a distribution power system. The aim is to determine the optimum dispatch schedules for an on-load tap changer (OLTC), distributed generator settings and all shunt capacitor switching on the load and DG generation profile in a day. The proposed method minimizes the real power losses and improves the voltage profile using squared deviations of bus voltages. The results indicate that the proposed method reduces the real losses and voltage fluctuations and improve receiving power factor. This paper proposes coordinated voltage and reactive power control methods that adjust optimal control values of capacitor banks, OLTC, and the AVR of DGs by using a voltage sensitivity factor (VSF) and dynamic programming (DP) with branch-and-bound (B&B) method. To avoid the computational burden, we try to limit the possible states to 24 stages by using a flexible searching space at each stage. Finally, we will show the effectiveness of the proposed method by using operational cost of real power losses and voltage deviation factor as evaluation index for a whole day in a power system with distributed generators.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.6
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• pp.58-62
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• 1985

Analytical threshold voltage model of small size ion-implanted MOSFET's is proposed. Yau's model which is only applicable to MOSFET's with constant doping concentration was modified to handle the MOSFET's with nonuniform channel doping concentration and bird's beak, whereby the short and narrow-channel effect was quantitively described. Threshold voltage model for short-channel MOSFET's was derived by approximating the SUPREM result of channel impurity profile to a 2-step profile, and the narrow width be-haviour was successfully described using thr'weighting factor'to accommodate the doping profile in the bird's beak region.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.4
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• pp.719-724
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• 2003

In this paper, we have presented the simulation results about threshold voltage of nano scale lightly doped drain (LDD) MOSFET with halo doping profile. Device size is scaled down from 100nm to 40nm using generalized scaling. We have investigated the threshold voltage for constant field scaling and constant voltage scaling using the Van Dort Quantum Correction Model (QM) and direct tunneling current for each gate oxide thickness. We know that threshold voltage is decreasing in the constant field scaling and increasing in the constant voltage scaling when gate length is reducing, and direct tunneling current is increasing when gate oxide thickness is reducing. To minimize the roll off characteristics for threshold voltage of MOSFET with decreasing channel length, we know $\alpha$ value must be nearly 1 in the generalized scaling.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.494-497
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• 2002

In this paper, we have presented the simulation results about threshold voltage of nano scale lightly doped drain (LDD) MOSFET with halo doping profile. Device size is scaled down from 100nm to 40nm using generalized scaling. We have investigated the threshold voltage for constant field scaling and constant voltage scaling using the Van Dort Quantum Correction Model(QM) and direct tunneling current for each gate oxide thickness. We know that threshold voltage is decreasing in the constant field scaling and increasing in the constant voltage scaling when gate length is reducing, and direct tunneling current is increasing when gate oxide thickness is reducing. To minimize the roll-off characteristics for threshold voltage of MOSFET with decreasing channel length, we know u value must be nearly 1 in the generalized scaling.

• Proceedings of the KIEE Conference
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• 2000.07a
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• pp.230-232
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• 2000

To improve the voltage profile of the load bus, it is important that the coordinated controls among the reactive power compensators at the distribution substation. However, the conventional control scheme of the Under Load Tap Changer (ULTC) is not proper for coordinate control with Static Var Compensator (SVC). This paper proposes a new control model for ULTC and a new coordinated control scheme between ULTC and SVC. The numerical simulation verifies that the proposed system could improve the voltage profile on the load bus and could decrease the number of ULTC tap operation.

• Journal of the Korean institute of surface engineering
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• v.32 no.3
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• pp.235-238
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• 1999

Silicon dioxide films were prepared by anodizing silicon wafers in an ethylene $glycol+HNO_3(0.04{\;}N)$ at 20 to $70^{\circ}C$. The voltage between silicon anode and platinum cathode was measured during this process. Under the constant current electrolysis, the voltage increased with oxide film growth. The transition time at which the voltage reached the predetermined value depended on the temperature of the electrolyte. After the time of electrolysis reached the transition time, the anodization was changed the constant voltage mode. The depth profile of oxide film/Si substrate was confirmed by XPS analysis to study the influence of the electrolyte temperature on the anodization. Usually, the oxide-silicon peaks disappear in the silicon substrate, however, this peak was not small at $45^{\circ}C$ in this region.