• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1543-1546
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• 2008

Modified pulse waveforms were applied to an AC plasma display panel with an auxiliary electrode in order to improve the operation voltage margin. Reciprocal sustain pulse waveforms and modified auxiliary pulse waveforms were applied to the sustain and auxiliary electrode, respectively. During the sustain period, the influence of the address electrode on the luminous efficacy of long-coplanar gap discharges was mitigated by application of reciprocal sustain pulse waveforms. Modified auxiliary pulse waveforms maintained the high efficacy obtained from the AC PDP with an auxiliary electrode. The proposed reciprocal sustain and modified auxiliary pulses waveforms can induce stable discharges in long-coplanar gap discharges and can control wall charges with a wider auxiliary pulse voltage margin, thereby enhancing the luminous efficacy of the AC PDP with an auxiliary electrode.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1191-1194
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• 2005

The effects of addition of $D_2$ to conventional gases on the discharge characteristics were investigated in this work with the aim of improving the voltage margin, the wall charge and the jitter. The addition of an extremely small gas-inlet amounts of $D_2$ increased the number of electrons which improves the $Xe^{\ast}$ density and $Xe_2^{\ast}$ density. As a result, the voltage margin, the jitter and the wall charge increased.

• ETRI Journal
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• v.29 no.4
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• pp.457-462
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• 2007

This work presents a low-voltage static random access memory (SRAM) technique based on a dual-boosted cell array. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin to a sufficient level without an increase in cell size. It also improves the SRAM circuit speed due to an increase in the cell read-out current. A 0.18 ${\mu}m$ CMOS 256-kbit SRAM macro is fabricated with the proposed technique, which demonstrates 0.8 V operation with 50 MHz while consuming 65 ${\mu}W$/MHz. It also demonstrates an 87% bit error rate reduction while operating with a 43% higher clock frequency compared with that of conventional SRAM.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.7
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• pp.23-29
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• 1997

The performance degradation of CMOS differential amplifiers due to hot carrier effect has been measured and analyzed. Two-state CMOS amplifiers whose input transistors are PMOSFETs were designed and fabriacted using the ISRC CMOS 1.5.mu.m process. It was observed after the amplifier was hot-carrier stressed that the small-signal voltage gain and the input offset voltage increased and the phase margin decreased. The performance variation results from the increase of the transconductances and gate capacitances of the PMOSFETs used as input transistors in the differential input stage and the output stage and also resulted from the decrease of their output conductances. After long-term stress, the amplifier became unstable. The reason might be that its phase margin was reduced due to hot carrier effect.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.3
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• pp.239-247
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• 2009

In AC-PDP, it is necessary to achieve high luminance efficacy, high luminance and high resolution by adopting technologies such as high Xenon concentration, MgO doping, and long gap. However, it is very difficult to apply above technologies because they reduce driving voltage margin. For example, doping of MgO reduces driving voltage but introduces new problems such as increased temperature dependency of discharge, which result in larger variations in driving margin at different temperatures. In this paper, we present the experimental results of the characteristics of temperature-dependent discharges. In addition, we suggest the mechanism of bright noise, black noise, and high temperature mis-discharge, which depend on temperature-dependent characteristics of MgO.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.12
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• pp.2370-2378
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• 2009

The enhanced phase angle estimation algorithm is essential to supply the power stably under synchronizing with grid source. In this paper, we are proposed the novel phase angle estimation algorithm and verified the validity of proposed method as simulation with PSIM and experiments. We sort the harmonics element using high-pass filter(HPF) that have the cut-off frequency below basic element and make reverse d-q transformation. So, it can be restored the harmonics element at stationary axis, and we can get the fundamental voltage element of AC grid. Proposed PLL method have a rapid responsibility and a large margin at controller design than conventional method because it have a small phase delay and a sufficient controller gain margin. And, it can reduce the error of voltage rms value and axis transformation according to robust PLL algorithm against the harmonic and phase unbalance.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.9-10
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• 2010

The lighting control power circuits should be designed in stable region according to the environment. A stable circuit is analyzed using ac equivalent circuits. The flyback converter with wide input voltage ranges is suitable for lighting control system. It is designed optimally for stability. The specifications are that the input voltage is 90V-230V, the output power is 12V/2.5A. The stability analysis is established using PSM(Phase Sensitive Multimeter) in experiment. As a result, it is confirmed that the gain margin and the phase margin are in stable area. The validity of the experimental measurement is verified.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.4
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• pp.176-181
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• 2001

As the data rate between chip-to-chip gets high, the skin effect and load of pins deteriorate noise margin. With these, noise disturbances on the bus channel make it difficult for receiver circuits to read the data signal. This paper has proposed a new pre-emphasis driver circuit which achieves wide noise margin by enlarging the signal voltage range during data transition. When data is transferred from a memory chip to a controller, the output boltage of the driver circuit reaches the final values through the intermediate voltage level. The proposed driver supplies more currents applicable to a packet-based memory system, because it needs no additional control signal and realizes very small area. The circuit has been designed in a 0.18 ${\mu}m$ CMOS process, and HSPICE simulation results have shown that the data rate of 1.32 Gbps be achieved. Due to its result, the proposed driver can achieved higher speed than conventional driver by 10%.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.260-263
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• 2001

In this paper, we experimentally considered the stability of AT forward MRC with the characteristics of high efficiency and high power density. The converter ratings are input 48V, output 5V/50W, The maximum voltage stress is measured to about 170V of 2 times the input voltage when the input is 58V. The $81.66\%$ of maximum efficiency could be obtained. For the stability of the converter, it is compensated through the error op amp in MC34067. A phase margin and a gain margin for relative stability are measured using HP4194A network analyzer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.506-507
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• 2005

The effects of addition of $D_2$ to conventional gases [Ne-Xe and He-Ne-Xe] on the discharge characteristics were investigated in this work with the aim of improving the voltage margin, the wall charge and the jitter. The addition of an extremely small gas-inlet amounts of $D_2$ increased the number of electrons which improves. the $Xe^*$ density and $Xe_2^*$ density. As a result, the voltage margin, the jitter and the wall charge increased.