• 한국전기전자재료학회논문지
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• 제18권9호
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• pp.815-820
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• 2005

ZnO varistor ceramics were fabricated with variation of addition of glass-frit amount and the sintering temperature was $1100^{\circ}C$. The average grain sizes were showed increased from $8.6{\mu}m\;to\;10{\mu}m$, and varistor voltages were decreased from 506V to 460V by added amount of glass-frit. Nonlinear coefficient $\alpha$, of all were with increasing the amount of glass-frit more than 70, in case of added on $0.03wt\%$ glass-frit was 83. And leakage current were less than $1{\mu}A$ with applied at $82\%$ of varistor voltage. The clamping voltage ratio of the specimens added $0.03wt\%$ glass-frit was 1.41 at applied 25A $[8/20\;{\mu}s]$. In the specimen added $0.03wt\%$ glass-frit, endurance of surge current and deviation of varistor voltage were $6200A/cm^2,\;\Delta-1.67\%$, respectively and clamping voltage ratio was 2.33. In the Specimen added $0.03wt\%$ glass-frit were superior to any other compositions on High Temperature Load Test(HTLT) for 1000 hr at $85^{\circ}C$, and deviation of the varistor voltage were $\Delta-1.29\%$.

• 대한기계학회논문집B
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• 제26권4호
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• pp.524-530
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• 2002

Micro electric spark discharge device was fabricated on a FOTURAN glass wafer using MEMS processing technique and its performance of electron discharge and subsequent formation of ignition kernel were tested. Micro electric spark device is an essential subsystem of a power MEMS that has been under development in this laboratories. In a combustion chamber of sub millimeter scale depth, spark electrodes are formed by electroplating Ni on a base plate of FOTURAN glass wafer. Optimization of spark voltage and spark gap is crucial for stable ignition and endurance of the electrodes. Namely, wider spark gaps insures stable ignition but requires higher ignition voltage to overcome the spark barrier. Also, electron discharge across larger voltage tends to erode the electrodes limiting the endurance of the overall system. In the present study, the discharge characteristics of the proptotype ignition device was measured in terms of electric quantities such as voltage and currant with spark gap and end shape as parameters. Discharge voltage shows a little decrease in width of less than 50㎛ and increases with electrode gap size. Reliability test shows no severe damage over 10$\^$6/ times of discharge test resulting in satisfactory performance for application to proposed power MEMS devices.

• 대한전기학회논문지
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• 제45권4호
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• pp.553-557
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• 1996

Heat cycle aging of insulating materials in large generator stator winding has been investigated using both on-line and off-line test methods. On this study, principally, off-line test against actual generator in service was carried out to acquire information about polarization index(PI) and dissipation factor, dissipation factor tip-up, maximum partial discharge for the purpose of remnant breakdown voltage and life assessment. It was found from the tests that both dissipation factor and maximum partial discharge decreased with the increase of operating hours and starting numbers. It was found from off-line tests that the remnant breakdown voltage had a strong relationship with both dissipation factor and maximum partial discharge the remnant breakdown voltage as a results of both operating hours and starting number and the nondestructive tests were proposed as parameters which can predict the remnant lifetime of insulating materials in large generator stator windings. (author). 8 refs., 8 figs., 2 tabs.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 추계종합학술대회 B
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• pp.604-607
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• 2008

본 연구에서는 NAND 플래시메모리를 위한 기본 셀로서 p채널 SONOS (silicon-oxide-nitride-oxide-silicon) 트랜지스터를 제작하고 이것의 메모리특성을 조사하였다. SONOS 트랜지스터의 제작은 $0.13{\mu}m$ low power용 standard logic 공정기술을 사용하였다. 게이트 절연막의 두께는 터널 산화막 $20{\AA}$, 질화막 $14{\AA}$, 그리고 블로킹산화막의 두께는 $49{\AA}$이다. 제작된 SONOS 트랜지스터는 낮은 쓰기/지우기 전압, 빠른 지우기 속도, 그리고 비교적 우수한 기억유지특성과 endurance 특성을 나타내었다.

• Transactions on Electrical and Electronic Materials
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• 제16권5호
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• pp.290-292
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• 2015

We have reported about bipolar resistive switching effect on Poly[2-methoxy-5-(2-ethylhexyloxy)-1,4-phenylenevinylene]:Graphene oxide composite films, which are sandwiched between aluminum and indium tin oxide electrodes. In this case, I-V sweep curve showed a hysteretic behavior, which varied according to the polarity of the applied voltage bias. The device exhibited excellent switching characteristics, with the ON/OFF ratio being approximately two orders in magnitude. The device had good endurance (10⁵ cycles without degradation) and long retention time (5 × 10³ s) at room temperature. The bistable switching behavior varied according to the trapping and de-trapping of charges on GO sites; the carrier transport was described using the space-charge-limited current (SCLC) model.

• 한국전기전자재료학회논문지
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• 제20권2호
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• pp.113-117
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• 2007

We have investigated the effects of doping concentration in polysilicon floating gate on the endurance characteristics of the EEPROM cell haying the structure of spacer select transistor. Several samples were prepared with different implantation conditions of phosphorus for the floating gate. Results show the dependence of doping concentration in polysilicon floating gate on performance of EEPROM cell from the floating gate engineering point of view. All of the samples were endured up to half million programming/erasing cycle. However, the best $program-{\Delta}V_{T}$ characteristic was obtained in the cell doped at the dose of $1{\times}10^{15}/cm^{2}$.

• 한국신뢰성학회:학술대회논문집
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• 한국신뢰성학회 2001년도 정기학술대회
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• pp.337-337
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• 2001

High voltage ceramic capacitors are widely applied in power electronic circuits, such as filters, snubbers, and resonant circuits, due to their excellent features of high voltage endurance and low aging. This paper presents a result of failure analysis and reliability evaluation for high voltage ceramic capacitors. The failure nodes and failure mechanisms were identified in order to understand the failure physics in a component. The causes of failure mechanisms for zero resistance phenomena under withstanding voltage test in high voltage ceramic capacitors molded by epoxy resin were studied by establishing an effective closed-loop failure analysis. Also, the condition for dielectric breakdown was investigated. Particular emphasis was placed on breakdown phenomena at the ceramic-epoxy interface. The validity of the results in this study was confirmed by the results of accelerated testing. Thermal shock test as well as pressure cooker test for high voltage ceramic capacitor mounted on a magnetron were implemented. Delamination between ceramic and epoxy, which, might cause electrical short in underlying circuitry, can occur during curing or thermal cycling. The results can be conveniently used to quickly identify defective lots, determine mean time to failure (MTTF) of each lot at the level of Inspection, and detect major changes in the vendors processes.

• 한국항공우주학회지
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• 제46권7호
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• pp.527-534
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• 2018

본 논문은 최근에 각광 받고 있는 드론(멀티콥터)과 관련하여 비행체의 비행 성능, 특히 비행 가능 시간에 대한 예측과 실험 데이터를 통한 검증 등을 목표로 하여, 제자리 비행에 대한 연구 결과를 제시 하고 있다. 연구 방법을 드론 시스템을 구성하고 있는 여러 부품들을 기능별로 분류하여 부품 수준에서의 제원과 기능에 대한 정리 및 수학적 수식화를 통하여 단위 부품의 성능을 분석 및 실험 데이터를 확보하고, 이들 단위 부품 데이터의 조합을 통하여 드론 시스템의 제자리비행 성능을 예측하는 연구 결과를 보여 주고 있다. 또한 5kg급 쿼드콥터를 이용하여 제자리 비행에 대한 분석을 통하여 비행시간에 따른 전압 변화를 예측, 검증 하였으며 해당 방법을 통해 제자리 비행시간을 예측하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.54-57
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• 2002

In this study, a new programming method, to minimize the generation of Si-SiO$_2$ interface traps of scaled SONOS flash memory as a function of number of program/erase cycles has been proposed. In the proposed programming method, power supply voltage is applied to the gate, forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim (MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and drain are open. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ prograss/erase cycles can be realized by the proposed programming method. The asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics of scaled SONOS devices because electrical stress applied to the Si-SiO$_2$ interface is reduced by short programming time.

• 한국전기전자재료학회논문지
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• 제16권1호
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• pp.5-10
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• 2003

In this study, a new programming method to minimize the generation of Si-SiO$_2$interface traps of SONOS nonvolatile memory device as a function of number of porgram/erase cycles was proposed. In the proposed programming method, power supply voltage is applied to the gate. forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim(MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and dram are left open. Also, the asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics or SONOS devices because electrical stress applied to the Si-SiO$_2$interface is reduced due to short program time.