• Journal of Korea Multimedia Society
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• v.14 no.1
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• pp.54-75
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• 2011

PoC(Push-to-talk Over Cellular) is an integrated technology of group voice calls, video calls and internet based multimedia services. If a PoC user can not participate in the PoC session for various reasons such as an emergency situation, lack of battery capacity, then the user can use the PoC Box which has a similar functionality to the MM Box in the MMS(Multimedia Messaging Service). The RTSP(Real-Time Streaming Protocol) method is recommended to be used when there is a transmission session between the PoC box and a terminal. Since the existing VOD service uses a wired network, the packet size of RTSP-based VOD service is huge, however, the PoC service has wireless communication environments which have general characteristics to be used in RTSP method. Packet loss in a wired communication environments is relatively less than that in wireless communication environment, therefore, a buffering latency occurs in PoC service due to a play-out delay which means an asynchronous play of audio & video contents. Those problems make a user to be difficult to find the information they want when the media contents are played-out. In this paper, the following techniques and methods were proposed and their performance and superiority were verified through testing: cross-over dual reception buffering technique, advance partition multi-reception buffering technique, and on-demand multi-reception buffering technique, which are designed for effective picking up of information in media content being transmitted in short amount of time using RTSP when a user searches for media, as well as for reduction in playback delay; and same-priority packetization transmission method and priority-based packetization transmission method, which are media data packetization methods for transmission. From the simulation of functional evaluation, we could find that the proposed multiple receiving buffering and packetizing methods are superior, with respect to the media retrieval inclination, to the existing single receiving buffering method by 6-9 points from the viewpoint of effectiveness and excellence. Among them, especially, on-demand multiple receiving buffering technology with same-priority packetization transmission method is able to manage the media search inclination promptly to the requests of users by showing superiority of 3-24 points above compared to other combination methods. In addition, users could find the information they want much quickly since large amount of informations are received in a focused media retrieval period within a short time.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.155-164
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• 2015

This paper describes a design and implementation of CABAC decoder, which would handle HEVC syntax elements in adaptively pipelined-parallel computation manner. Even though CABAC offers the high compression rate, it is limited in decoding performance due to context-based sequential computation, and strong data dependency between context models, as well as decoding procedure bin by bin. In order to enhance the decoding computation of HEVC CABAC, the flag-type syntax elements are adaptively pipelined by precomputing consecutive flag-type ones; and multi-bin syntax elements are decoded by processing bins in parallel up to three. Further, in order to accelerate Binary Arithmetic Decoder by reducing the critical path delay, the update and renormalization of context modeling are precomputed parallel for the cases of LPS as well as MPS, and then the context modeling renewal is selected by the precedent decoding result. It is simulated that the new HEVC CABAC architecture could achieve the max. performance of 1.01 bins/cycle, which is two times faster with respect to the conventional approach. In ASIC design with 65nm library, the CABAC architecture would handle 224 Mbins/sec, which could decode QFHD HEVC video data in real time.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.17-26
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• 2016

This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7B
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• pp.598-612
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• 2004

Client requests have increased with the improvement of network resources at client side, whereas network resources at server side could not keep pace with the increased client request. Therefore, it is primary factor of the Qos that efficiently utilize network resources at server side. In this paper, we proposed a new model that peer-to-peer transfer scheme for partial multimedia stream based on CIWP which it decrease server network bandwidth by utilizing client disk resources saves additional server network resources. Especially, adapting Threshold_Based Multicast scheme guarantees to do that data transfer within clients never exceed service time of previous peer by restriction of which data size transferring from previous peer less than data size transferring from server. Peer-to-peer transfer within clients is limited in same group classified as ISPs. Our analytical result shows that proposed scheme reduces appling network resources at server side as utilizing additional client disk resource. furthermore, we perform various simulation study demonstrating the performance gain through comparing delay time and proportion of waiting requesters. As a result, when we compared to Threshold_Based Multicast scheme, the proposed scheme reduces server network bandwidth by 35%.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.4
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• pp.17-27
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• 2007

The enhanced distributed channel access (EDCA) of IEEE 802.11e has been standardized for supporting Quality of Service (QoS) in wireless LANs. In the EDCA, support of QoS can be achieved statistically by reducing the probability of medium access for lower priority traffics. In other words, it provides statistical channel access rather than deterministically prioritized access to high priority traffic. Therefore, lower priority traffics affect the performance of higher priority traffics. Consequently, at the high loads, the EDCA does not guarantee the QoS of multimedia applications such as voice and video even though it provides higher priority. In this paper, we propose a simple and effective scheme, called deterministic priority channel access (DPCA), for improving the QoS performance of the EDCA mechanism. In order to provide guaranteed priority channel access to multimedia applications, the proposed scheme uses a busy tone for limiting the transmissions of lower priority traffics when higher priority traffic has data packets to send. Performance of the proposed scheme is investigated by numerical analysis and simulation. Our results show that the proposed scheme outperforms the EDCA in terms of throughput, delay, jitter, and drop under a wide range of contention levels.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.2
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• pp.81-89
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• 2008

Wideband speech, characterized by a bandwidth of about 7 kHz (50-7000 Hz), provides a substantial quality improvement in terms of naturalness and intelligibility. Although higher data rates are required, it has extended its application to audio and video conferencing, high-quality multimedia communications in mobile links or packet-switched transmissions, and digital AM broadcasting. In this paper, we present a new bandwidth-scalable coder for wideband speech and audio signals. The proposed coder spits 8kHz signal bandwidth into two narrow bands, and different coding schemes are applied to each band. The lower-band signal is coded using the ITU-T G.729/G.729E coder, and the higher-band signal is compressed using a new algorithm based on the gammatone filter bank with an invertible auditory model. Due to the split-band architecture and completely independent coding schemes for each band, the output speech of the decoder can be selected to be a narrowband or wideband according to the channel condition. Subjective tests showed that, for wideband speech and audio signals, the proposed coder at 14.2/18 kbit/s produces superior quality to ITU-T 24 kbit/s G.722.1 with the shorter algorithmic delay.

• Journal of Advanced Marine Engineering and Technology
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• v.40 no.7
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• pp.613-621
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• 2016

This research connected network equipment, including CCTV, PAGA, IP-PBX, and Legacy, in order to enable the operation and configuration of internal IP-based network equipment in maritime plants and vessels, both in the field and from remote places, and to allow for the support of remotely controlling such equipment. It also realized an operating program for the integrated network equipment management system to enable the monitoring and control of equipment status, operation condition, and notifications from distant places. By applying the operating program to satellite stations and vessels sailing on the sea, a performance test was conducted to evaluate data loss and transmission/reception delay in the communication section between the land and vessels. As a result, this research verified the normal operation of CCTV control and of real-time monitoring and control of the network equipment, including PAGA, IP-PBX, and Legacy under the FBB and MVSAT environments. It was observed that the transmission of CCTV video images with a large volume of data as well as the transmission and reception of voice data were found to be slightly delayed, indicating the need to develop technology to compress and convert data for real-time transmission and reception.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.4
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• pp.2749-2756
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• 2015

Recently, Depending on the quality of data increases, the problem of time-consuming to process the image is raised by being required to accelerate the image processing algorithms, in a traditional CPU and CUDA(Compute Unified Device Architecture) based recognition system for computing speed and performance gains compared to OpenMP When character recognition has been learned by the system to measure the input by the character data matching is implemented in an environment that recognizes the region of the well, so that the font of the characters image learning English alphabet are each constant and standardized in size and character an image matching method for calculating the matching has also been implemented. GPGPU (General Purpose GPU) programming platform technology when using the CUDA computing techniques to recognize and use the four cores of Intel i5 2500 with OpenMP to deal quickly and efficiently an algorithm, than the performance of existing CPU does not produce the rate of four times due to the delay of the data of the partition and merge operation proposed a method of improving the rate of speed of about 3.2 times, and the parallel processing of the video card that processes a result, the sequential operation of the process compared to CPU-based who performed the performance gain is about 21 tiems improvement in was confirmed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.56-63
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• 2010

This work proposes a 12b 100MS/s 0.13um CMOS pipeline ADC for battery-powered mobile video applications such as DVB-Handheld (DVB-H), DVB-Terrestrial (DVB-T), Satellite DMB (SDMB), and Terrestrial DMB (TDMB) requiring high resolution, low power, and small size at high speed. The proposed ADC employs a three-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. A single shared and switched op-amp for two MDACs removes a memory effect and a switching time delay, resulting in a fast signal settling. A two-step reference selection scheme for the last-stage 6b FLASH ADC reduces power consumption and chip area by 50%. The prototype ADC in a 0.13um 1P7M CMOS technology demonstrates a measured DNL and INL within 0.40LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 60.0dB and a maximum SFDR of 72.4dB at 100MS/s, respectively. The ADC with an active die area of 0.92 $mm^2$ consumes 24mW at 1.0V and 100MS/s. The FOM, power/($f_s{\times}2^{ENOB}$), of 0.29pJ/conv. is the lowest of ever reported 12b 100MS/s ADCs.