• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.12C
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• pp.1173-1183
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• 2006

In this paper, we propose an efficient method for improving visual quality of AR-FGS (Adaptive Reference FGS) which is adopted as a key scheme for SVC (Scalable Video Coding) or H.264 scalable extension. The standard FGS (Fine Granularity Scalability) adopts AR-FGS that introduces temporal prediction into FGS layer by using a high quality reference signal which is constructed by the weighted average between the base layer reconstructed imageand enhancement reference to improve the coding efficiency in the FGS layer. However, when the enhancement stream is truncated at certain bitstream position in transmission, the rest of the data of the FGS layer will not be available at the FGS decoder. Thus the most noticeable problem of using the enhancement layer in prediction is the degraded visual quality caused by drifting because of the mismatch between the reference frame used by the FGS encoder and that by the decoder. To solve this problem, we exploit the principle of cyclical block coding that is used to encode quantized transform coefficients in a cyclical manner in the FGS layer. Encoding block coefficients in a cyclical manner places 'higher-value' bits earlier in the bitstream. The quantized transform coefficients included in the ealry coding cycle of cyclical block coding have higher probability to be correctly received and decoded than the others included in the later cycle of the cyclical block coding. Therefore, we can minimize visual quality degradation caused by bitstream truncation by adjusting weighting factor to control the contribution of the bitstream produced in each coding cycle of cyclical block coding when constructing the enhancement layer reference frame. It is shown by simulations that the improved AR-FGS scheme outperforms the standard AR-FGS by about 1 dB in maximum in the reconstructed visual quality.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.5
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• pp.46-54
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• 2011

In this paper, we propose a low-complexity loop filtering method depending on transform-block regions. Block adaptive loop filter (BALF) was developed to improve about 10% in compression performance for the next generation video coding. The BALF employs the Wiener filter that makes reconstructed frames close to the original ones and transmits filter-related information. However, the BALF requires high computational complexity, while it can achieve high compression performance because the block adaptive loop filter is applied to all the pixels in blocks. The proposed method is a new loop filter that classifies pixels in a block into inner and boundary regions based on the characteristics of the integer transform and derives optimum filters for each region. Then, it applies the selected filters for the inner and/or boundary regions. The decoder complexity can be adjusted by selecting region-dependent filter to be used in the decoder side. We found that the proposed algorithm can reduce 35.5% of computational complexity with 2.56% of compression loss, in case that only boundary filter is used.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.102-111
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Motion Compensation in 4K UHD($3840{\times}2160$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $9{\times}9$ reference data for interpolation, we design 2D cache buffer which consists of the $9{\times}9$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The maximum operation frequency is 150MHz. The gate count is 161Kgates. The proposed H.264/AVC Motion Compensation can support 4K UHD at 72 frames per second by running at 150MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.619-630
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• 2003

We present a method of runtime configuration scheduling in reconfigurable SoC design. As a model of computation, we use a popular formal model of computation, hierarchical FSM (HFSM) with synchronous dataflow (SDF) model, in short, HFSM-SDF model. In reconfigurable SoC design with HFSM-SDF model, the problem of configuration scheduling becomes challenging due to the dynamic behavior of the system such as concurrent execution of state transitions (by AND relation), complex control flow (HFSM), and complex schedules of SDF actor firing. This makes it hard to hide configuration latency efficiently with compile-time static configuration scheduling. To resolve the problem, it is necessary to know the exact order of required configurations during runtime and to perform runtime configuration scheduling. To obtain the exact order of configurations, we exploit the inherent property of HFSM-SDF that the execution order of SDF actors can be determined before executing the state transition of top FSM. After obtaining the order information and storing it in the ready configuration queue (ready CQ), we execute the state transition. During the execution, whenever there is FPGA resource available, a new configuration is selected from the ready CQ and fetched by the runtime configuration scheduler. We applied the method to an MPEG4 decoder and IS95 design and obtained up to 21.8% improvement in system runtime with a negligible overhead of memory usage.

• Journal of KIISE:Computing Practices and Letters
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• v.10 no.4
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• pp.309-318
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• 2004

This paper proposes the H.264-based selective fine granular scalable (FGS) coding scheme that selectively uses the temporal prediction data in the enhancement layer. The base layer of the proposed scheme is basically coded by the H.264 (MPEG-4 Part 10 AVC) visual coding scheme that is the state-of-art in codig efficiency. The enhancement layer is basically coded by the same bitplane-based algorithm of the MPEG-4 (Part 2) fine granular scalable coding scheme. In this paper, we introduce a new algorithm that uses the temproal prediction mechanism inside the enhancement layer and the effective selection mechanism to decide whether the temporally-predicted data would be sent to the decoder or not. Whenever applying the temporal prediction inside the enhancement layer, the temporal redundancies may be effectively reduced, however the drift problem would be severly occurred especially at the low bitrate transmission, due to the mismatch bewteen the encoder's and decoder's reference frame images. Proposed algorithm selectively uses the temporal-prediction data inside the enhancement layer only in case those data could siginificantly reduce the temporal redundancies, to minimize the drift error and thus to improve the overall coding efficiency. Simulation results, based on several test image sequences, show that the proposed scheme has 1∼3 dB higher coding efficiency than the H.264-based FGS coding scheme, even 3∼5 dB higher coding efficiency than the MPEG-4 FGS international standard.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.1
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• pp.43-50
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• 2005

We proposed a method for embedding coded binary data into EZW bitstreams and extracting embedded data from EZW bitstreams using the traditional EZW decoder. EZW coder have two passes. The first pass, the dominant pass have four symbols, P, N, IZ, ZTR. The second pass is sub-ordinary pass which specifies the value of symbol. In the proposed methods, we use ZTR symbol in the dominant pass. We embed watermark into ZTR symbol in the highest frequency band which original image is transferred by wavelet transform. The proposed digital watermarking method shows good properties for robustness in the low bit rate. Accordingly, based on the proposed digital watermarking, video and 3D image watermarking will become a new area for research in the near future.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.1
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• pp.25-32
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• 2004

Nowadays image processing is very useful for some field of traffic applications. The one reason is we can construct the system in a low price, the other is the improvement of hardware processing power, it can be more fast to processing the data. In traffic field, the development of image using system is interesting issue. Because it has the advantage of price of installation and it does not obstruct traffic during the installation. In this study, 1 propose the traffic monitoring system that implement on the embedded system environment. The whole system consists of two main part, one is host controller board, the other is image processing board. The part of host controller board take charge of control the total system interface of external environment, and OSD(On screen display). The part of image processing board takes charge of image input and output using video encoder and decoder, Image classification and memory control of using FPGA, control of mouse signal. And finally, for stable operation of host controller board, uC/OS-II operating system is ported on the board.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.1
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• pp.1-9
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into a H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel for the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks. The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit or a field synchronized with the A/D converter. The implemented H/W used the 54％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation. that is. processing 60 fields/sec(30 frames/sec).

• Journal of Korea Multimedia Society
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• v.2 no.3
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• pp.265-276
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• 1999

Video on Demand (VOD) system is definitely one of main applications in upcoming multimedia era. In this research, we have designed and implemented a host-based scalable VOD system (SVOD) which is composed of low cost PC servers and runs on Linux kernel that is currently spotlighted in enterprise and research domains. Our contribution is as follows: first, the previous Ext2 file system was modified to efficiently support continuous media like MPEG stream. Second, the storage server features a host-based scalable architecture. Third, a software MPEG decoder was implemented using Microsoft's DirectShow$\circledR$COM. Finally, flow control between client and server is provided to suppress overflow and underflow of client circular buffer and supports FF VCR operation. We have known that it is possible to develop a thread-based and scalable VOD system on low cost PC servers and free Linux kernel.

• Journal of Broadcast Engineering
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• v.17 no.2
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• pp.422-425
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• 2012

This paper proposes the CU-based approach for merge candidate list construction for providing reduced complexity and improved parallelism compared to the PU-based one. In the proposed method, a CU can have only one merge candidate list. So, Only one common merge candidate list is used for all PUs in a CU regardless of the PU partition type. The simulation results of proposed method showed that the encoder computational complexity was decreased by 3% to 6% and the decoder computational complexity was negligible change with the penalty of roughly 0.2% - 0.5% coding loss. The proposed method has several advantages: it provides simpler design, reduced complexity, and improved parallelism.