• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.925-931
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• 2008

In video coding standard H.264/AVC, variable block size mode algorithm improves compression efficiency but has need of a large amount of computation for various block modes and mode decision. Meanwhile, decided inter block modes depend on the complexity of a block image, and then the more complex a macroblock is, the smaller its block size is. This paper proposes fast inter block mode decision algorithm. It limits valid block modes to the block modes with a great chance for decision using the image complexity and carries out motion estimation rate-distortion optimization with only the valid block modes. In addition to that, it applies fast motion estimation PDE to the valid block modes with only the $16{\times}16$ block mode. The reference software JM 9.5 was executed to estimate the proposed algorithm's performance. The simulation results showed that the proposed algorithm could save about 24.12% of the averaged motion estimation time while keeping the image quality and the bit rate to be -0.02dB and -0.12% on the average, respectively.

• 한국방재학회:학술대회논문집
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• 2008.02a
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• pp.75-78
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• 2008

Limit states of a tension member are the yielding of gross section, fracture of net section, and block shear failure. Block shear failure is very complicated than other limit state because of interaction of tension and shear failure. Block shear failure is studied continuously since the 1970s. However, failure model to estimate the strength of block shear failure provided in current design specifications is not reflective of the failure mode observed in the various experimental studies. Comparisons between the experimental results and design rules in various specifications about the block shear failure were conducted in this study. Also, the need for further studies of block shear failure were proposed.

• Journal of Sensor Science and Technology
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• v.24 no.2
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• pp.124-130
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• 2015

This paper presents a high performance HIGHT processor that can be applicable for CCM mode. In fact, HIGHT algorithm is a 64-bit block cipher. However, the proposed HIGHT extends the basic block length to 128-bit. The proposed HIGHT is operated as 128-bit block cipher and it can treat 128-bit block at once. Thus, it can be applicable for the various WSN applications that need fast and ultralight 128-bit block cipher, in particular, to be operated in CCM mode. In addition, the proposed HIGHT processor shares the common logics such as 128-bit key scheduler and control logics during encryption and decryption to reduce the area overhead caused by the extension of data block length. From the simulation results, the circuit area and power consumption of the proposed HIGHT are increases as 40% and 64% compared to the conventional 64-bit counterpart. However, the throughput of the proposed HIGHT can be up to two times as fast. Consequently, the proposed HIGHT is useful for USN and handheld devices based on battery as well as RFID tag the size of circuit is less than 5,000 gates.

• Journal of Broadcast Engineering
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• v.25 no.5
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• pp.698-708
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• 2020

VVC (Versatile Video Coding), which has been developing as a next generation video coding standard. Compared to HEVC (High Efficiency Video Coding), VVC is improved by about 34% in RA (Random Access) configuration and about 30% in LDB (Low-Delay B) configuration by adopting various techniques such as recursive block partitioning structure and GPM (Geometric Partitioning Mode). But the encoding complexity is increased by about 10x and 7x, respectively. In this paper, we propose a fast decision method of GPM mode and block partitioning using directionality of block to reduce encoding complexity of VVC. The proposed method is to apply the Hough transform to the current block to identify the directionality of the block, thereby determining the GPM mode and the specific block partitioning method to be skipped in the rate-distortion cost search process. As a result, compared to VTM8.0, the proposed method reduces about 31.01% and 29.84% encoding complexity for RA and LDB configuration with 2.48% and 2.69% BD-rate loss, respectively.

• Journal of the Korean Society for Precision Engineering
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• v.11 no.6
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• pp.65-74
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• 1994

Various substructure synthesis methods, such as component mode synthesis, building block analysis and reduced impedance method, are studied for the determination of vibration characteristics of plate problems. Comparisons are made for each methods in terms of accuracy and computational efficiency. Following conclusions are made from the results of computer simulations and experiments. i) The computation time of component mode synthesis is much shorter than that of whole structure analysis. The natural frequencies of lower modes obtained from component mode synthesis are almost same as those obtained from whole structure analysis, but in higher modes the differences between those two methods are increases. ii) The transfer function obtained from building block analysis is same as that obtained from the finite element method. iii) Same transfer functions can be obtained by the reduced impedance method. The computation time of reduced impedance mathod is shorter that that of general finite element method, but for the solutions in broad frequency band it requires long calculation time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1C
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• pp.56-62
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• 2009

In H.264/AVC, rate distortion optimization algorithm is used to decide the best block mode from various block modes. It improves a bit rate but greatly increases an amount of computation. This paper proposes a fast rate distortion optimization algorithm that omits a rate distortion optimization adaptively by predicting its cost from the cost calculated for motion estimation. The simulation results show that the proposed algorithm, on average, keeps nearly the image quality and the bit rate made by the rate distortion optimization while reduces 69.86% and 69.63% of computation added by it in CIF and QCIF respectively.

• ETRI Journal
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• v.37 no.6
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• pp.1176-1187
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• 2015

This work proposes a highly efficient sensorless motor driver chip for various permanent-magnet synchronous motors (PMSMs) in a wide power range. The motor driver chip is composed of two important parts. The digital part is a sensorless controller consisting mainly of an angle estimation block and a speed control block. The analog part consists of a gate driver, which is able to sense the phase current of a motor. The sensorless algorithms adapted in this paper include a sliding mode observer (SMO) method that has high robust characteristics regarding parameter variations of PMSMs. Fabricated SMO chips detect back electromotive force signals. Furthermore, motor current-sensing blocks are included with a 10-bit successive approximation analog-to-digital converter and various gain current amplifiers for proper sensorless operations. Through a fabricated SMO chip, we were able to demonstrate rated powers of 32 W, 200 W, and 1,500 W.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.4
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• pp.588-594
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• 2021

SIMON, a lightweight block cipher developed by the US National Security Agency, is a family of block ciphers optimized for hardware implementation. It supports many kinds of standards to operate in various environments. The counter mode of operation is one of the operational modes. It provides to encrypt plaintext which is longer than the original size. The counter mode uses a constant(Nonce) and Counter value as an input value. Since Nonce is the identical for all blocks, so it always has same result when operates with other constant values. With this feature, it is possible to skip some instructions of round function by pre-computation. In general, the input value of SIMON is affected by the counter. However in an 8-bit environment, it is calculated in 8-bit units, so there is a part that can be pre-computed. In this paper, we focus the part that can be pre-calculated, and compare with previous works.

• Journal of Broadcast Engineering
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• v.25 no.3
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• pp.338-345
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• 2020

Versatile Video Coding (VVC), which has been developing as a next generation video coding standard, has adopted various techniques to achieve more than twice the compression performance of HEVC (High Efficiency Video Coding). The recently released VVC Test Model (VTM) shows 38% Bjontegaard Delta bitrate (BD-rate) improvement and 9x/1.6x encoding/decoding complexity over HEVC. In order to reduce such increased complexity, various fast algorithms have been proposed. In this paper, gradient-based methods of fast intra mode decision and block splitting are presented. Experimental results show that, compared to VTM6.0, the proposed method gives up to 65% encoding time reduction with 3.54% BD-rate loss in All-Intra (AI) configuration.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.141-146
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• 2016

HEVC/H.265 is the latest joint video coding standard proposed by ITU-T SG 16 WP and ISO/IEC JTC 1/SC29/WG 11. In H.265, pictures are divided into a sequence of coding tree units(CTUs), and the CTU further is partitioned into multiple CUs to adapt to various local characteristics. Its coding efficiency is approximately two times high compared to previous standard H.264/AVC. However according to the size of extended CU(coding unit) and transform block, the hardware size of PMR(prediction/mode decision/reconstruction) block within video encoder is about 4 times larger than previous standard. In this study, we propose a new less complex hardware architecture of PMR block which has the most high complexity within encoder without any noticeable PSNR loss. Using this simplified block, we can shrink the overall size the H.265 encoder. For FHD image, it operates at clocking frequency of 300 MHz and frame rate of 60 fps. And also for the test image, the Bjøntegaard Delta (BD) bit rate increase about average 30 % in PMR prediction block, and the total estimated gate count of PMR block is around 1.8 M.