• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.10
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• pp.1845-1852
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• 2008

The key elements of inter prediction are motion estimation(ME) and motion compensation(MC). Motion estimation is to find the optimum motion vectors, not only by using a distance criteria like the SAD, but also by taking into account the resulting number of 비트s in the 비트 stream. Motion compensation is compensate for movement of blocks of current frame. Inter-prediction Encoding is always the main bottleneck in high-quality streaming applications. Therefore, in real-time streaming applications, dedicated hardware for executing Inter-prediction is required. In this paper, we studied a motion estimator(ME) for H.264/AVC. The designed motion estimator is based on 2-D systolic array and it connects processing elements for fast SAD(Sum of Absolute Difference) calculation in parallel. By providing different path for the upper and lower lesion of each reference data and adjusting the input sequence, consecutive calculation for motion estimation is executed without pipeline stall. With data reuse technique, it reduces memory access, and there is no extra delay for finding optimal partitions and motion vectors. The motion estimator supports variable-block size and takes 328 cycles for macro-block calculation. The proposed architecture is local memory-free different from paper [6] using local memory. This motion estimation encoder can be applicable to real-time video processing.

• ETRI Journal
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• v.26 no.3
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• pp.229-240
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• 2004

This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.102-107
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• 2007

This paper proposes a H.264/AVC entropy decoder without embedded processor nor memory fabrication process. Many researches on H.264/AVC entropy decoders require ROM or RAM fabrication process, which is difficult to be implemented in general digital logic fabrication process. Furthermore, many researches require embedded processors for bitstream manipulation, which increases area and power consumption. This papers proposes hardwired H.264/AVC entropy decoder without embedded processor, which improves data processing speed and reduces power consumption. Furthermore, its CAVLC decoder optimizes lookup table and internal buffer without embedded memory, which reduces hardware size and can be implemented in general digital logic fabrication process without ROM or RAM fabrication process. Designed entropy decoder was embedded in H.264/AVC video decoder, and it was verified to operate correctly in the system. Synthesized in TSMC 90nm fabrication process, its maximum operation frequency is 125MHz. It supports QCIF, CIF, and QVGA image format. Under slight modification of nC register and other blocks, it also support VGA image format.

• Transactions of the Korean Society of Automotive Engineers
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• v.18 no.1
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• pp.14-22
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• 2010

Hybrid Electronic Vehicle (HEV) is one of the solutions of high oil price and environment problem. Recently, study of HEV is important for automobile industry. However HEV has a lot of components and there are many cases for assembling, it's impossible to test results from assembling by using real vehicles. To solve this problem, hybrid system simulator is required. The purpose of this study is to develop and optimize of engine module for hybrid system simulator. The commercial 1-D engine simulation program, WAVE is used to get the engine capacity and performance data and 1-D simulation model of base engine is compared with engine experiment results. Using the data, the engine module is developed based on the MATLAB Simulink. There are blocks of base engine, Single-CVVT engine and Dual-CVVT engine. The effect of acceleration and deceleration is applied to each engine block. In addition, the control and processing logics for CIS technology are developed. Finally the simulator operates FTP-72 mode test.

• The Korean Journal of Pain
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• v.31 no.3
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• pp.155-173
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• 2018

Chronic postsurgical pain (CPSP) is an unwanted adverse event in any operation. It leads to functional limitations and psychological trauma for patients, and leaves the operative team with feelings of failure and humiliation. Therefore, it is crucial that preventive strategies for CPSP are considered in high-risk operations. Various techniques have been implemented to reduce the risk with variable success. Identifying the risk factors for each patient and applying a timely preventive strategy may help patients avoid the distress of chronic pain. The preventive strategies include modification of the surgical technique, good pain control throughout the perioperative period, and preoperative psychological intervention focusing on the psychosocial and cognitive risk factors. Appropriate management of CPSP patients is also necessary to reduce their suffering. CPSP usually has a neuropathic pain component; therefore, the current recommendations are based on data on chronic neuropathic pain. Hence, voltage-dependent calcium channel antagonists, antidepressants, topical lidocaine and topical capsaicin are the main pharmacological treatments. Paracetamol, NSAIDs and weak opioids can be used according to symptom severity, but strong opioids should be used with great caution and are not recommended. Other drugs that may be helpful are ketamine, clonidine, and intravenous lidocaine infusion. For patients with failed pharmacological treatment, consideration should be given to pain interventions; examples include transcutaneous electrical nerve stimulation, botulinum toxin injections, pulsed radiofrequency, nerve blocks, nerve ablation, neuromodulation and surgical management. Physical therapy, cognitive behavioral therapy and lifestyle modifications are also useful for relieving the pain and distress experienced by CPSP patients.

• Environmental and Resource Economics Review
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• v.23 no.3
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• pp.409-434
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• 2014

This paper estimates household demand for electricity using a micro-level household expenditure data set. A two-stage estimation method where the endogenous block price estimates are obtained from a discrete block choice model is used. This method successfully identifies a downward sloping conditional demand function with the data, while both the usual two-stage method with instrumental variable estimation and the Hewitt-Hanemann discrete-continuous model fail to do that. The paper simulates the impacts of two hypothetical pricing reforms that reduce the number of blocks and make the price gap smaller. It is shown that the reform may increase the overall consumer benefit, but is regressive.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.5 s.311
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• pp.72-78
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• 2006

In this paper, we present a video shot retrieval algorithm in H.264/AVC compression domain. Unlike previous standards such as MPEG-2 and 4, H.264/AVC supports a variable block size for motion compensation. Therefore, existing video retrieval algorithms exploiting the motion vectors in MPEG-2 and 4 domains are not appropriate for H.264/AVC. So, we devise a method to project motion vectors with larger than $4{\times}4$ block sizes into those for the smallest $4{\times}4$ blocks. It also uses correlations among features for the measure of similarity. Experimental results with standard videos of 10558 frames and commercial videos of 48161 frames show that the proposed method yields ANMRR less than 0.2.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.48-54
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• 2010

This paper presents a high-performance architecture of integer-pel motion estimation circuit for H.264 video CODEC. Full search algorithm guarantees the best results by examining all candidate blocks. However, the full search algorithm requires a huge amount of computation and data. Many fast search algorithms have been proposed to reduce the computational efforts. The disadvantage of these algorithms is that data access from or to memory is very irregular and data reuse is difficult. In this paper, we propose an efficient integer-pixel motion estimation algorithm and the circuit architecture to improve the processing speed and reduce the external memory bandwidth. The proposed circuit supports seven kinds of variable block sizes and generates 41 motion vectors. We described the proposed high-performance motion estimation circuit at R1L and verified its operation on FPGA board. The circuit synthesized by using l30nm CMOS standard cell library processes 139.8 1080HD ($1,920{\times}1,088$) image frames per second and supports up to H.264 level 5.1.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.1
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• pp.23-30
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• 2010

The H.264/AVC is increasingly used in broadcast video applications such as Internet Protocol television (IPTV), digital multimedia broadcasting (DMB) because of high compression performance. But the H.264/AVC coded video can be delivered to the widespread end-user equipment for MPEG-2 after transcoding between this video standards. This paper suggests a new transcoding algorithm for H.264/AVC to MPEG-2 transcoder that uses motion vector clustering in order to reduce the complexity without loss of video quality. The proposed method is exploiting the motion information gathered during h.264 decoding stage. To reduce the search space for the MPEG-2 motion estimation, the predictive motion vector is selected with a least distortion of the candidated motion vectors. These candidate motion vectors are considering the correlation of direction and distance of motion vectors of variable blocks in H.264/AVC. And then the best predictive motion vector is refined with full-search in ${\pm}2$ pixel search area. Compared with a cascaded decoder-encoder, the proposed transcoder achieves computational complexity savings up to 64% with a similar PSNR at the constant bitrate(CBR).

• Journal of Internet Computing and Services
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• v.11 no.2
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• pp.49-60
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• 2010

H.264/AVC offers a better encoding efficiency than conventional video standards by adopting many new encoding techniques. However, the advanced coding techniques also add to the overall complexity for H.264/AVC encoder. Accordingly, it is necessary to perform optimization to alleviate the level of complexity for the video encoder. The amount of computation for motion estimation is of particular importance. In this paper, we propose a diamond web-grid search algorithm combined with efficient stationary block skip method which employs full diamond and dodecagon search patterns, and the variable thresholds are used for performing an effective skip of stationary blocks. The experimental results indicate that the proposed technique reduces the computations of the unsymmetrical-cross multi-hexagon-grid search algorithm by up to 12% while maintaining a similar PSNR performance.