• International Journal of Internet, Broadcasting and Communication
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• 제12권1호
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• pp.90-94
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• 2020

Artificial intelligence (AI) is software that learns large amounts of data and provides the desired results for certain patterns. In other words, learning a large amount of data is very important, and the role of memory in terms of computing systems is important. Massive data means wider bandwidth, and the design of the memory system that can provide it becomes even more important. Providing wide bandwidth in AI systems is also related to power consumption. AlphaGo, for example, consumes 170 kW of power using 1202 CPUs and 176 GPUs. Since more than 50% of the consumption of memory is usually used by system chips, a lot of investment is being made in memory technology for AI chips. MRAM, PRAM, ReRAM and Hybrid RAM are mainly studied. This study presents various memory technologies that are being studied in artificial intelligence chip design. Especially, MRAM and PRAM are commerciallized for the next generation memory. They have two significant advantages that are ultra low power consumption and nearly zero leakage power. This paper describes a comparative analysis of the four representative new memory technologies.

• 한국산업정보학회논문지
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• 제19권1호
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• pp.61-67
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• 2014

센서 시스템과 같은 저전력 설계를 요구하는 시스템에서 기존의 동기방식의 회로는 낮은 전압에서 지연(delay)이 급격히 증가하여 시스템의 전체 성능을 유지할 수 없을 뿐만 아니라, 공정, 전압, 온도 변이 (PVT variation), 노화 등에 크게 영향을 받아서 올바른 동작을 기대할 수 없다. 따라서, 신뢰할 수 있는 초저전력 설계에서 비동기 회로가 스케일링 이슈를 해결할 수 있는 방법으로 최근 다시 고려되고 있다. 그러나, 디지털 시스템에서 동기회로를 NCL 회로로 모두 대체하는 것은 쉽지가 않기때문에 동기회로와 비동기 회로 사이의 연결이 꼭 필요하다. 본 논문에서는 동기회로와 비동기 회로를 연결할 수 있는 새로운 설계방법을 보이고, 0.18um 공정기술을 사용한 $4{\times}4$ 곱셈기를 사용해서 검증을 하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 I
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• pp.446-449
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• 2003

In recent years, the research of an efficient transmission method is going to meet a demand for high speed and large capacity radio communication. These systems make use of ultra-short duration pulses which yield UWB(Ultra Wide Band) signals characterized by low power spectral densities. The wavelet synthesis wave is able to set up the scale freely. So it is possible to use as the transmission wave of UWB by compressing time. In this paper, we present a general analytical expression for the average BER(Bit Error Rate) performance of UWB data transmission using wavelet system as a function of the cross-correlation between the users' signatures in an additive white Gaussian noise(AWGN) channel.

• International Journal of Internet, Broadcasting and Communication
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• 제13권1호
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• pp.69-81
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• 2021

While the fifth generation (5G) and beyond 5G (B5G) mobile communication networks are being rolled over the globe, several world-wide companies have already started to prepare the sixth generation (6G). Such 6G mobile networks targets ultra-reliable low-latency communication (URLLC). In this paper, we challenge to reduce the inherent latency of existing non-orthogonal multiple access (NOMA) in 5G networks of massive connectivity. First, we propose the novel unipodal binary pulse amplitude modulation (2PAM) NOMA, especially without SIC, which greatly reduce the latency in existing NOMA. Then, the achievable data rates for the unipodal 2PAM NOMA are derived. It is shown that for unequal gain channels, the sum rate of the unipodal 2PAM NOMA is comparable to that of the standard 2PAM NOMA, whereas for equal gain channels, the sum rate of the unipodal 2PAM NOMA is superior to that of the standard 2PAM NOMA. In result, the unipodal 2PAM could be a promising modulation scheme for NOMA systems toward 6G.

• ETRI Journal
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• 제32권1호
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• pp.1-10
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• 2010

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-$2^4$ algorithm and a radix-$2^3$ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 ${\mu}m$ CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

• 한국멀티미디어학회논문지
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• 제17권5호
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• pp.573-581
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• 2014

The salient features of UWB(Ultra WideBand) networks such as high-rate communications, low interference with other radio systems, and low power consumption bring many benefits to users, thus enabling several new applications such as wireless universal serial bus (WUSB) for connecting personal computers (PCs) to their peripherals and the consumer-electronics (CE) in people's living rooms. Because the size of multimedia data frame, WiMedia device must transmit the fragment of MSDU. However, when the fragment of MSDU is lost, WiMedia device maintains active mode for the time to complete the transmission MSDU, and there is a problem that unnecessary power consumption occurs. Therefore we propose new power management scheme to reduce unnecessary power consumption of WiMedia devices in the case that the fragment is lost.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.745-753
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• 2016

This paper presents a fully synthesizable low power interconnect bus for millimeter-scale wireless sensor nodes. A segmented ring bus topology minimizes the required chip real estate with low input/output pad count for ultra-small form factors. By avoiding the conventional open drain-based solution, the bus can be fully synthesizable. Low power is achieved by obviating a need for local oscillators in member nodes. Also, aggressive power gating allows low-power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with a power management unit that has nW standby mode. A 3-module system including the bus is fabricated in a 180 nm process. The entire system consumes 8 nW in standby mode, and the bus achieves 17.5 pJ/bit/chip.

• 한국산업정보학회논문지
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• 제21권1호
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• pp.17-25
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• 2016

본 논문은 동기회로에서 누설 전류를 줄이기 위해서 사용되는 파워 스위치 구조를 결합한 새로운 구조의 저전력 비동기 회로 설계 방법을 제안하고자 한다. Static 방식, Semi-static 방식과 같은 기존의 지연 무관방식의 비동기 방식과 비교해서 다소 속도의 손해는 있지만, 파워 스위치에 의해서 데이터가 없는 상태에서는 누설 전력을 줄일 수 있고, 전체 사이즈가 작아짐으로써 데이터가 입력되는 순간의 스위칭 전력도 줄일 수 있는 장점이 있다. 따라서, 제안된 방법은 속도보다 저전력을 기본으로 하는 사물인터넷 시스템에서 요구되는 전전력 설계 방법이 될 것이다. 본 논문에서는 새로운 방식의 비동기 회로를 사용하여 $4{\times}4$곱셈기를 0.11um 공정으로 설계하고, 기존의 비동기 방식의 곱셈기와 스피드, 누설 전류, 스위칭 파워, 회로 크기 등을 비교하였다.

• 대한전자공학회논문지TC
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• 제45권11호
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• pp.61-68
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• 2008

본 논문은 차량용 UWB 레이더 시스템의 RF front-end 개발에 그 목적이 있다. UWB 시스템은 1ns 이하의 매우 좁은 펄스폭을 갖는 임펄스를 전송한다. 따라서 수 GHz에 이르는 매우 낮은 전력의 초광대역 특성을 갖게 되어 기존의 무선 통신 시스템과의 공존이 불가피하다. UWB의 장점은 높은 채널 용량과 데이터 전송률을 가지며, 다중 경로에 대한 세밀한 분해가 용이하여 위치 예측과 Rake 수신이 가능하다는 점이다. 또한 UWB는 저전력의 초광대역 특성을 나타내므로 낮은 간섭 특성을 가지며, 초단거리의 정밀함에 의해 위치 추적이 가능하며, 시스템 구현 비용을 절감할 수 있다. RF front-end 모듈은 DCR(Direct ConveRsion) 방식을 사용하여 설계하였으며, 저가의 차량용 RF단에 적합하게 구성을 하였다.

• 전자통신동향분석
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• 제38권1호
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• pp.36-45
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• 2023

The increasing demand for ultra-high efficiency of compact power conversion systems for electric vehicle applications has brought GaN power semiconductors to the fore due to their low conduction losses and fast switching speed. In particular, the development of materials and core device processes contributed to remarkable results regarding the publication of vertical GaN power devices with high breakdown voltage. This paper reviews recent advances on GaN material technology and vertical GaN power device technology. The GaN material technology covers the latest technological trends and GaN epitaxial growth technology, while the vertical GaN power device technology examines diodes, Trench FETs, JFETs, and FinFETs and reviews the vertical GaN PiN diode technology developed by ETRI.