• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.425-435
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• 2016

This paper describes a spread-spectrum clock generation method by utilizing a ${\Delta}{\Sigma}$ digital PLL (DPLL) which is solely based on binary phase detection and does not require a linear time-to-digital converter (TDC) or other linear digital-to-time converter (DTC) circuitry. A 1-bit high-order ${\Delta}{\Sigma}$ modulator and a hybrid finite-impulse response (FIR) filter are employed to mitigate the phase-folding problem caused by the nonlinearity of the bang-bang phase detector (BBPD). The ${\Delta}{\Sigma}$ DPLL employs a two-point modulation technique to further enhance linearity at the turning point of a triangular modulation profile. We also show that the two-point modulation is useful for the BBPLL to improve the spread-spectrum performance by suppressing the frequency deviation at the input of the BBPD, thus reducing the peak phase deviation. Based on the proposed architecture, a 3.2 GHz spread-spectrum clock generator (SSCG) is implemented in 65 nm CMOS. Experimental results show that the proposed SSCG achieves peak power reductions of 18.5 dB and 11 dB with 10 kHz and 100 kHz resolution bandwidths respectively, consuming 6.34 mW from a 1 V supply.

• Journal of Electrical Engineering and Technology
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• v.12 no.2
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• pp.738-750
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• 2017

In this paper, carrier-based pulse width modulation (CBPWM), space vector PWM (SVPWM) and reduced switching losses PWM (RSLPWM) for the three-level neutral point clamped (NPC) inverter are introduced. In the case of the neutral point (NP) potential (NPP) offset, an asymmetric disposition PWM (ASPDPWM) strategy is proposed, which can output PWM sequences correctly and suppress the lower order harmonics of the inverter effectively. An NPP balance strategy based on carrier based PWM (CBPWM) is analyzed. A hybrid modulation strategy combining RSLPWM and the NPP balance based on CBPWM is proposed, and hysteresis control is adopted to switch between the two modulation strategies. An experimental prototype of the three-level NPC inverter is built. The effectiveness of the hybrid modulation is verified with a resistance-inductance load and a permanent magnetic synchronous motor (PMSM) load, respectively. The experimental results show that reduced switching losses and an acceptable NPP can be effectively achieved in the hybrid modulation strategy.

• Journal of Electrical Engineering and Technology
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• v.9 no.2
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• pp.489-500
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• 2014

This paper presents a simple modified unipolar carrier-based pulsewidth modulation (CB-PWM) strategy for the three-level neutral-point-clamped (NPC) voltage source inverter (VSI). Analytical expressions for the relationship between modulation reference signals and output voltages are derived. The proposed modulation technique for the three-level NPC VSI includes the maximum and minimum of the three-phase sinusoidal reference voltages with zero-sequence voltage injection concept. The proposed modified CB-PWM strategy incorporates a novel method that requires only of one triangular carrier wave for generate the gating pulses in three-level NPC VSI. It has the advantages of being simplifying the algorithm with no need of complex two/multi-carrier pulsewidth modulation or space vector modulation (SVM) and it's also simple to implement. The possibility of the proposed CB-PWM technique has been verified though computer simulation and experimental results.

• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.1986-1995
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• 2018

In this paper, a novel neutral-point voltage balancing scheme for NPC three-level inverters using carrier-based sinusoidal pulse width modulation (SPWM) method is developed. The new modulation approach, based on the obtained expressions of zero sequence voltage in all six sectors, can significantly suppress the low-frequency voltage oscillation in the neutral point at high modulation index and achieve a fast voltage-balancing dynamic performance. The implementation of the proposed method is very simple. Another attractive feature is that the scheme can stably control any voltage difference between the two dc-link capacitors within a certain range without using any extra hardware. Furthermore, the presented scheme is also applicable to the single-phase NPC three-level inverter. It can maintain the neutral-point voltage balance at full modulation index and improve the voltage-balancing dynamic performance of the single-phase NPC three-level inverter. The performance of the proposed strategy and its benefits over other previous techniques are verified experimentally.

• Journal of Power Electronics
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• v.19 no.3
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• pp.727-743
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• 2019

This paper presents a pulse-width modulation strategy to eliminate the common mode voltage (CMV) with reduced CMV spikes in multilevel inverters since a high CMV magnitude and its fast variations dv/dt result in bearing failure of motors, overvoltage at motor terminals, and electromagnetic interference (EMI). The proposed method only utilizes the zero CMV states in a space vector diagram and it is implemented by a carrier-based pulse-width modulation (CBPWM) method. This method is generalized for odd number levels of inverters including neutral-point-clamped (NPC) and cascaded H-bridge inverters. Then it is extended to the over-modulation mode. The over-modulation mode is implemented by using the two-limit trajectory principle to maintain linear control and to avoid look-up tables. Even though the CMV is eliminated, CMV spikes that can cause EMI and bearing current problems still exist due to the deadtime effect. As a result, the deadtime effect is analyzed. By taking the deadtime effect into consideration, the proposed method is capable of reducing CMV spikes. Simulation and experimental results verify the effectiveness of the proposed strategy.

• Journal of Power Electronics
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• v.19 no.4
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• pp.944-955
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• 2019

In this paper, the three-level T-type neutral-point-clamped indirect matrix converter topology and the relative space vector modulation methods are introduced to improve the voltage transfer ratio and output voltage performance. The presented converter topology is based on combinations of cascaded-rectifier and three-level T-type neutral-point-clamp inverter. It can overcome the limitation of voltage transfer ratio of the conventional matrix converter and the high voltage rating of power switches of conventional matrix converter. Two SVPWM strategies for proposed converter are described in this paper to achieve the advantages features such as: sinusoidal input/output currents and three-level output voltage waveforms. Results from Psim 9.0 software simulation are provided to confirm the theoretical analysis. Hence, a laboratory prototype was implemented, and the experimental results are shown to validate the simulation results and to verify the effectiveness of the proposed topology and modulation strategies.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.247-255
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• 2011

This paper describes a CMOS outphasing transmitter using two wideband phase modulators. The proposed architecture can simplify the overall outphasing transmitter architecture using two-point phase modulation in phase-locked loop, which eliminates the necessity digital-to-analog converters, filters, and mixers. This architecture is verified with a WCDMA signal at 1.65 GHz. The prototype is fabricated in standard 130 nm CMOS technology. The measurement results satisfied the spectrum mask and 4.9% EVM performance.

• Journal of Sensor Science and Technology
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• v.29 no.3
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• pp.180-186
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• 2020

In this study, we applied edge-pulse modulation to prevent the flicker of light-emitting diode (LED) light in a visible light identification system. In the visible light transmitter, positive pulses were transmitted at the edges of the low-to-high transition points, and negative pulses were transmitted at the edges of the high-to-low transition points of the non-return-to-zero (NRZ) data waveforms. In the visible light receiver, the NRZ waveforms were regenerated by making low-to-high and high-to-low transitions at the point of the positive and negative pulses, respectively. This method has two advantages. First, it ensures that the LED light is flicker-free because the average optical power of the LED was kept constant during data transmission in the transmitter. Second, the 120 Hz optical noise from the adjacent lighting lamps was easily cut off using a simple RC-high pass filter in the receiver.

• Journal of Power Electronics
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• v.18 no.2
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• pp.445-455
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• 2018

A novel algorithm is proposed to regulate the neutral point potential in neutral point clamped three-level inverters. Oscillations of the neutral point potential and an unbalanced dc-link voltage cause distortions of the output voltage. Large capacitors, which make the application costly and bulky, are needed to eliminate oscillations. Thus, the algorithm proposed in this paper utilizes the finite-control-set model predictive control and the multistage medium vector to solve these issues. The proposed strategy consists of a two-step prediction and a cost function to evaluate the selected multistage medium vector. Unlike the virtual vector method, the multistage medium vector is a mixture of the virtual vector and the original vector. In addition, its amplitude is variable. The neutral point current generated by it can be used to adjust the neutral point potential. When compared with the virtual vector method, the multistage medium vector contributes to decreasing the regulation time when the modulation index is high. The vectors are rearranged to cope with the variable switching frequency of the model predictive control. Simulation and experimental results verify the validity of the proposed strategy.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.291.1-291.1
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• 2016

Graphene by one of the two-dimensional (2D) materials has been focused on electronic applications due to its ultrahigh carrier mobility, outstanding thermal conductivity and superior optical properties. Although graphene has many remarkable properties, graphene devices have low on/off current ratio due to its zero bandgap. Despite considerable efforts to open its bandgap, it's hard to obtain appropriate improvements. To solve this problem, heterojunction barristor was proposed based on graphene. Mostly, this heterojunction barristor is made by transition metal dichalcogenides (TMDs), such as molybdenum disulfide ($MoS_2$) and tungsten diselenide ($WSe_2$), which have extremely thickness scalability of TMDs. The heterojunction barristor has the advantage of controlling graphene's Fermi level by applying gate bias, resulting in barrier height modulation between graphene interface and semiconductor. However, charged impurities between graphene and $SiO_2$ cause unexpected p-type doping of graphene. The graphene's Fermi level modulation is expected to be reduced due to this p-doping effect. Charged impurities make carrier mobility in graphene reduced and modulation of graphene's Fermi level limited. In this paper, we investigated theoretically and experimentally a relevance between graphene's Fermi level and p-type doping. Theoretically, when Fermi level is placed at the Dirac point, larger graphene's Fermi level modulation was calculated between -20 V and +20 V of $V_{GS}$. On the contrary, graphene's Fermi level modulation was 0.11 eV when Fermi level is far away from the Dirac point in the same range. Then, we produced two types heterojunction barristors which made by p-type doped graphene and graphene treated 2.4% APTES, respectively. On/off current ratio (32-fold) of graphene treated 2.4% APTES was improved in comparison with p-type doped graphene.