• Journal of Power Electronics
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• v.12 no.4
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• pp.528-537
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• 2012

This paper presents an interleaved resonant converter with a parallel-series transformer connection in order to achieve ripple current reduction at the output capacitor, zero voltage turn-on for the active switches, zero current turn-off for the rectifier diodes, less voltage stress on the rectifier diodes, and less current stress on the transformer primary windings. The primary windings of the two transformers are connected in parallel in order to share the input current and to reduce the root-mean-square (rms) current on the primary windings. The secondary windings of the two transformers are connected in series in order to ensure that the transformer primary currents are balanced. A full-wave diode rectifier is used at the output side to clamp the voltage stress of the rectifier diode at the output voltage. Two circuit modules are operated with the interleaved PWM scheme so that the input and output ripple currents are reduced. Based on the resonant behavior, all of the active switches are turned on under zero voltage switching (ZVS), and the rectifier diodes are turned off under zero current switching (ZCS) if the operating switching frequency is less than the series resonant frequency. Finally, experiments with a 1kW prototype are described to verify the effectiveness of the proposed converter.

• International Commerce and Information Review
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• v.9 no.2
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• pp.423-439
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• 2007

The purpose of this study was to analyze market competitiveness of Korean and Chinese computer parts industry in the between two countries' market by using Index of Export Bias and Market Comparative Advantage Index. For attaining the purpose of study, we classified the computer parts which exported to the two countries' market and the imported products as the memory devices and input/output peripheral devices. Analyzing period was 2001-2006. The analysis of Korean results of Index of Export Bias indicated that memory devices represented low overall numerical value and the Chinese results of Index of Export Bias indicated that memory devices represented high gradual numerical value. On the other hand, Korean input/output peripheral devices have been increasing steadily for analysis period and China input/output peripheral devices have been decreasing steadily for analysis period. Additional results indicated that the Korean and China computer parts which gained market competitiveness between two countries market were as follows. Korean memory devices have been losing competitiveness in the China market steadily and Chinese memory devices have been acquire competitiveness in the Korean market gradually. In input/output peripheral devices case, Korean products represented powerful competitiveness in the China market and Chinese products have been gaining competitiveness in the Korea market.

• Journal of Power Electronics
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• v.1 no.2
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• pp.78-87
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• 2001

A new high-power step-up based on the two-module parallel-input (PISO) modular dual inductor-fed push-pull converter is proposed. The proposed converter is operated at a constant duty cycle and employs and auxiliary circuit to control the output voltage with a phase-shift between two modules. It shows a high efficiency due to the greatly reduced switch turn-off stress. It also shows a high and linear voltage conversion ratio, low current stress in the output capacitor, and fast control-to-output dynamics. The operation principles and the mathematical models of the proposed converter are presented. Features of the proposed converter are discussed in comparison with the two-module PISO modular dual inductor-fed push-pull converter. Also, experimental results from a 50kHz, 800W, 350 Vdc prototype with an input voltage range of 20-32 Vdc are provided to confirm the validity of the proposed converter. The new converter compares favorably with the conventional counterpart, and is considered well siuted to high-power step-up applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.5
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• pp.963-969
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• 2000

In this paper, we define two input-output gains of linear periodic time-varying systems. One is the ratio of output with worst-case l2-norm over all inputs with unit 12-norm. It denotes G($\iota_2,\iota_2$.The other is the ratio of output with worst-case RMS value over all inputs with unit RMS value. It denotes G(RMS, RMS) .It is fact that these two gains are equivalent for linear time-invariant system. In this paper, we prove these two gains are also equivalent for linear periodic time-varying system. In addition, the relationship between two method of obtaining the generalized frequency responses for linear periodic time-varying system is derived. Finally, we apply the defined input-output gains to M-channel filter-bank which is multi-rate signal Processing system, used to speech coding. In the filter-bank, generally, aliasing distortion, magnitude distortion, and phase distortion are present. It is shown that these are kept small if the filter-bank is designed by a method that optimizes the gain G($\iota_2,\iota_2$ of an error system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.8 no.4
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• pp.323-331
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• 1997

In this paper, the high efficiency balanced amplifier is presented as high efficiency power amplifier. This amplifier is basically composed of two FETs, an input power divider, output power combiner, input matching circuits, output matching circuits, second harmonic interconnection circuit and lowpass filter. The second harmonic interconnection circuit is composed of second harmonic frequency bandpass filter and transmission line. This circuit is inserted between the output terminals of the two FEF's output matching circuit, there is a second harmonic standing wave generated between two FET outputs. The electric wall termination is equivalent to the short circuit termination. As a result, the FET output termination condition needed to attain high efficiency is realized. Experimental high efficiency balanced amplifier is constructed to determine its practically attainable efficiency. The input VSWR is 1.27, and the output VSWR is 1.18. Power added efficiency of 75% is attained at 1.75 GHz band about 3W to balanced amplifier.

• Journal of Sensor Science and Technology
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• v.32 no.4
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• pp.223-231
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• 2023

An integrated-optical biochemical sensor structure that can perform homogeneous and surface sensing using a 2×2 balanced-bridge Mach-Zehnder interference structure based on the optimized SOI slot optical waveguide was described, and its performance and characteristics were evaluated. Equations for the two output optical powers were derived and examined using the transfer matrices of a 3-dB coupler and phase shifter (channel waveguide). The length of the 3-dB coupler was determined such that the two output optical powers were same using these formulas. In homogeneous sensing, the effect of the refractive index of an analyte in the range of 1.33-1.36 on the two output optical power distributions was numerically derived, and the sensitivity was calculated based on each output and the difference between the two outputs, the former and the latter being 7.5796-19.0305 [au/RIU] and 15.2601-38.1351 [au/RIU], respectively. In the case of surface sensing, the sensitivity range of the refractive index of 1.337 based on each of the two outputs was calculated as -2.2490--3.5854 [au/RIU] and 1.2194-3.8012 [au/RIU], and the sensitivity range of 4.8048-7.0694 [au/RIU] was confirmed based on the difference between the two outputs.

• Journal of KIISE:Software and Applications
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• v.32 no.12
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• pp.1260-1270
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• 2005

Support Vector Machines (SVM) is well known for a representative learner as one of the kernel methods. SVM which is based on the statistical learning theory shows good generalization performance and has been applied to various pattern recognition problems. However, SVM is basically to deal with a two-class classification problem, so we cannot solve directly a multi-class problem with a binary SVM. One-Per-Class (OPC) and All-Pairs have been applied to solve the face recognition problem, which is one of the multi-class problems, with SVM. The two methods above are ones of the output coding methods, a general approach for solving multi-class problem with multiple binary classifiers, which decomposes a complex multi-class problem into a set of binary problems and then reconstructs the outputs of binary classifiers for each binary problem. In this paper, we introduce the output coding methods as an approach for extending binary SVM to multi-class SVM and propose new output coding schemes based on the Error-Correcting Output Codes (ECOC) which is a dominant theoretical foundation of the output coding methods. From the experiment on the face recognition, we give empirical results on the properties of output coding methods including our proposed ones.

• Journal of Power Electronics
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• v.17 no.3
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• pp.632-640
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• 2017

Input series output independent (ISOI) dc-dc converter systems are suitable for high voltage input and multiple output applications with low voltage rating switches. This paper proposes a novel control strategy consisting of one output voltage regulating (OVR) control loop and n-1 (n is the number of modules in the ISOI system) input voltage sharing (IVS) control loops. An ISOI system with the proposed control strategy can be applied to applications where the output loads of each module are the same. Under these conditions, IVS can be achieved and output voltages copying can be realized in an ISOI system. In this control strategy there is only one controller for each module and the design process of the control loops is simple. Since no central controller is needed in the system, modularity of the system is improved. The operation principle of the new control strategy is introduced and the control effect is simulated. Then the output power and voltage characteristics of an ISOI system under this new control strategy are analyzed. The stability of the proposed control strategy is explored base on a Hurwitz criterion, and the design guide line of the control strategy is given. A two module ISOI system prototype is fabricated and tested in the laboratory. Experimental results verify the effectiveness of the proposed control strategy.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.2
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• pp.1-9
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• 1998

ATM was adopted as the switching and multiplexing technique for BISDN which aims at transmitting traffics with various characteristics in a unified network. To construct these ATM networks, the most important aspect is the design of the switching system with high performance and different service capabilities. In this paepr, we analyze the performance of an input and output queueing switch with preemptive priority which is considered to be most suitable for ATM networks. For the analysis of an input queue, we model each input queue as two separate virtual input queues for each priority class and we approximage them asindependent Geom/Geom/1 queues. And we model a virtual HOL queue which consists of HOL cells of all virtual input queues which have the same output address to obtain the mean service time at each virtual input queue. For the analysis of an output quque, we obtain approximately the arrival process into the output queue from the state of the virtual HOL queue. We use a Markov chain method to analyze these two models and obtain the maximum throughput of the switch and the mean queueing delay of cells. and analysis results are compared with simulation to verify that out model yields accurate results.

• Journal of Electrical Engineering and Technology
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• v.11 no.1
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• pp.143-149
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• 2016

The two-stage converter is widely used in traditional DC/AC inverter. It has several disadvantages such as complex topology, large volume and high loss. In order to overcome these shortcomings, a novel half load-cycle worked dual SEPIC single-stage inverter, which is based on the analysis of the relationship between input and output voltages of SEPIC converters operating in the discontinuous conduction mode (DCM), is presented in this paper. The traditional single-stage inverter has remarkable advantages in small and medium power applications, but it can’t realize boost DC/AC output directly. Besides one pre-boost DC/DC converter is needed between the DC source and the traditional single-stage inverter. A novel DC/AC inverter without pre-boost DC/DC converter, which is comprised of two SEPIC converters, is studied. The output of dual SEPIC converters is connected with anti-parallel and half load-cycle control is used to realize boost and buck DC/AC output directly and work properly, whatever the DC input voltage is higher or lower than the AC output voltage. The working principle, parameter selection and the control strategy of the inverters are analyzed in this paper. Simulation and experiment results verify the feasibility of the new inverter.