• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.318-321
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• 2009

We have studied transparent top gate Al-Zn-Sn-O (AZTO) TFTs with an $Al_2O_3$ protective layer (PL) on an active layer. We also fabricated a transparent 2.5 inch QCIF+AMOLED display panel using the AZTO TFT back-plane. The AZTO active layers were deposited by RF magnetron sputtering at room temperature and the PL was deposited by ALD with two different processes. The mobility and subthreshold slope were superior in the cases of the vacuum annealing and the oxygen plasma PL compared to the $O_2$ annealing and the water vapor PL, however, the bias stability was excellent for the TFTs of the $O_2$ annealing and the water vapor PL.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.7
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• pp.545-549
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• 2010

Low-frequency noise (1/f noise) has been measured in order to analyze the Vth instability of ZnO TFTs having two different active layer thicknesses of 40 nm and 80 nm. Under electrical stress, it was found that the TFTs with the active layer thickness of 80 nm shows smaller threshold voltage shift (${\Delta}V_{th}$) than those with thickness of 40 nm. However the ${\Delta}V_{th}$ is completely relaxed after the removal of DC stress. In order to investigate the cause of this threshold voltage instability, we accomplished the 1/f noise measurement and found that ZnO TFTs exposed the mobility fluctuation properties, in which the noise level increases as the gate bias rises and the normalized drain current noise level($S_{ID}/{I_D}^2$) of the active layer of thickness 80 nm is smaller than that of active layer thickness of thickness 40 nm. This result means that the 80 nm thickness TFTs have a smaller density of traps. This result correlated with the physical characteristics analysis performmed using XRD, which indicated that the grain size increases when the active layer thickness is made thicker. Consequently, the number of preexisting traps in the device increases with decreasing thickness of the active layer and are related closely to the $V_{th}$ instability under electrical stress.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.45-52
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• 2009

We proposed a new pixel circuit and driving method for the large-area, high-luminance AMOLED applications in this study. We designed with the low-temperature poly-silicon(LTPS) thin film transistors(TFTs) that has poor uniformity but stable characteristic. To improve the uniformity of an image, the threshold voltage($V_{TH}$) and the mobility of the TFTs can be compensated together. The proposed method overcomes the previous methods for mobility compensation, and that is profitable for large-area applications. Black data insertion was introduced to improve the characteristics for moving images. AMOLED panel can operate in two compensation mode, so the luminance degradation by mobility compensation can be released. The scan driver for controlling the pixel circuits were optimized, and the compensation mode can be controlled simply by that. Final driving signal has large timing margin, and the panel operates stably. The pixel circuit was designed for 14.1" WXGA top-emission ANGLED panel. The non-uniformity of the designed panel was estimated under 5% for the mobility compensation time of 1us.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1546-1548
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• 2002

In this paper, the electrical characteristics of pentacene thin film transistors(TFTs) with stacked and surface-treated gate insulators have been investigated. The semiconductor layer of pentacene was thermally evaporated onto the stacked gate insulators. For the gate insulating materials. PVP(PolyvinylPhenol) and polystyrene were spin-coated with two different stacking orders, PVP-polystyrene and polystyrene-PVP. Rapid solvent evaporation during the spin-coating processes of these insulating layers produces non-equilibrium phase morphologies accompanied by surface undulations on gate insulator interfaces. This non-equilibrium phase morphology affects the growth mode of the subsequent pentacene layer. Therefore, in order to smoothen the gate dielectric surfaces, gate dielectric surfaces were rubbed laterally along the direction from the drain to the source TFTs with with stacked and surface-treated gate insulators have provided improved operational characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.287-287
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• 2010

We report a new direct patterning method, called liquid bridge-mediated nanotransfer molding (LB-nTM), for the formation of two- or three-dimensional structures with feature sizes between tens of nanometers and tens of micron over large areas. LB-nTM is based on the direct transfer of various materials from a mold to a substrate via a liquid bridge between them. This procedure can be adopted for automated direct printing machines that generate patterns of functional materials with a wide range of feature sizes on diverse substrates. Arrays of TIPS-PEN TFTs were fabricated on 4" polyethersulfone (PES) substrates by LB-nTM using PDMS molds. An inverted staggered structure was employed in the TFT device fabrication. A 150 nm-thick indium-tin oxide (ITO) gate electrode and a 200 nm-thick SiO2dielectric layer were formed on a PES substrate by sputter deposition. An array of TIPS-PEN patterns (thickness: 60 nm) as active channel layers was fabricated on the substrate by LB-nTM. The nominal channel length of the TIPS-PEN TFT was 10 mm, while the channel width was 135 mm. Finally, the source and drain electrodes of 200 nm-thick Ag were defined on the substrate by LB-nTM. The TIPS-PEN TFTs can endure strenuous bending and are also transparent in the visible range, and therefore potentially useful for flexible and invisible electronics.

• Proceedings of the KIEE Conference
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• 2000.11c
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• pp.455-457
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• 2000

In this work the electrical characteristics of organic TFTs with the semiconductor-insulator interfaces, where the gate dielectrics were treated by the two methods which are the deposition of Octadecyltrichlorosilane (OTS) on the insulator and rubbing the insulator surface. Pentacene is used as an active semiconducting layer. The semiconductor layer of pentacene was thermally evaporated in vacuum at a pressure of about $2{\times}10^{-7}$ Torr and at a deposition rate of $0.3{\AA}/sec$. Aluminum and gold were used for the gate and source/drain electrodes. OTS is used as a self-alignment layer between $SiO_2$ and pentacene. The gate dielectric surface was rubbed before pentacene is deposited on the insulator. In order to confirm the changes of the surface morphology the atomic force microscopy (AFM) was utilized. The characteristics of the fabricated TFTs are measured to clarify the effects of the surface treatment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.151-151
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• 2009

Recently, there has been increasing interest in amorphous oxide semiconductors to find alternative materials for an amorphous silicon or organic semiconductor layer as a channel in thin film transistors(TFTs) for transparent electronic devices owing to their high mobility and low photo-sensitivity. The fabriction of amorphous oxide-based TFTs at room temperature on plastic substrates is a key technology to realize transparent flexible electronics. Amorphous oxides allows for controllable conductivity, which permits it to be used both as a transparent semiconductor or conductor, and so to be used both as active and source/drain layers in TFTs. One of the materials that is being responsible for this revolution in the electronics is indium-zinc-tin oxide(IZTO). Since this is relatively new material, it is important to study the properties of room-temperature deposited IZTO thin films and exploration in a possible integration of the material in flexible TFT devices. In this research, we deposited IZTO thin films on polyethylene naphthalate substrate at room temperature by using magnetron sputtering system and investigated their properties. Furthermore, we revealed the fabrication and characteristics of top-gate-type transparent TFTs with IZTO layers, seen in Fig. 1. The experimental results show that by varying the oxygen flow rate during deposition, it can be prepared the IZTO thin films of two-types; One a conductive film that exhibits a resistivity of $2\times10^{-4}$ ohm${\cdot}$cm; the other, semiconductor film with a resistivity of 9 ohm${\cdot}$cm. The TFT devices with IZTO layers are optically transparent in visible region and operate in enhancement mode. The threshold voltage, field effect mobility, on-off current ratio, and sub-threshold slope of the TFT are -0.5 V, $7.2\;cm^2/Vs$, $\sim10^7$ and 0.2 V/decade, respectively. These results will contribute to applications of select TFT to transparent flexible electronics.

• Journal of the Korean Society for Heat Treatment
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• v.21 no.1
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• pp.3-9
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• 2008

Al-Co-N thin films, Al-Co-N/Al-N and Al-Co-N/Al-Co multilayers containing various amounts of Co content were deposited by using a two-facing targets type dc sputtering (TFTS) system. The films were also annealed successively and isothermally at different annealing temperatures. Irrespective of Co content and preparation methods, all the as-deposited films were observed non-magnetized. It was found that annealing conditions can control the magnetic and electrical properties as well as the microstructure of the films.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.826-829
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• 2009

The authors report on the fabrication of p-type depletion mode inverter that composed of two pentacene based thin-film transistors (TFTs) on several dielectric surfaces. We use shift of threshold voltage depends on pentacene-thickness.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.911-914
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• 2007

We developed the laser annealing system using green laser of 261W(5kHz) and 75.5mJ/pulse(2kHz). We confirmed that this system makes it possible to form two kinds(large or uniformed grain) of poly-Si by changing its polarized directions. By using ${\mu}-crystal-Si$ as irradiated films, grain size uniformity is better than that using a-Si.