• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1996년도 추계학술대회 논문집
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• pp.13-17
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• 1996

Superthin ONO ( oxide -nitride - oxide ) structures were fabricated for the MONOS nonvolatile memory device with a 20$\AA$ tunneling oxide, 40$\AA$ nitride and 40$\AA$ blocking oxide. The compositions of each layer in a superthin ONO structure were investigated. Also, the characteristics of trap related to the memory quality were examined.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.199-199
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• 2008

이 실험은 NVM의 Oxide, Nitride, Oxide nitride층별 blocking, trapping and tunneling 속성에 대해서 밝히고자 한다. gate 전극은 값싸고 전도도가 좋은 알루미늄을 사용한다. 유리기판위에 Silicon nitride층을 20nm로 코팅하고 Silicon dioxide층을 10nm로 코팅한다. 그리고 amorphous Silicon material이 증착된다. Poly Silicon은 Solid Phase Crystallization 방법을 사용하였다. 마지막 공정으로 p-doping은 ion shower에 의한 방법으로 drain과 source 전극을 생성하였다. gate가 biasing 될 때, p-channel은 source와 drain 사이에서 형성된다. Oxide Nitride Oxide nitride (ONO) 층은 각각 12.5nm/20nm/2.3nm의 두께로 만들었다. 전하는 Program process 중에 poly Silicon층에서 Silicon Oxide nitride tunneling층을 통하여 움직이게 된다. 그리고 전하들은 Silicon Nitride층에 머무르게 된다. 그 전하들은 erasing process 중에 trapping 층에서 poly Silicon 층으로 되돌아 간다. Silicon Oxide blocking층은 trapping층으로 전하가 나가는 것을 피하기 위하여 더해진다. 이 논문에서 Programming process와 erasing process의 Id-Vg 특성곡선을 설명한다. Programming process에 positive voltage를 또는 erasing process에 negative voltage를 적용할 때, Id-Vg 특성 곡선은 왼쪽 또는 오른쪽으로 이동한다. 이 실험이 보여준 결과값에 의해서 10년 이상의 저장능력이 있는 메모리를 만들 수 있다. 그러므로, NVM의 중요한 두 가지 성질은 유지성과 내구성이다.

• E2M - 전기 전자와 첨단 소재
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• 제10권1호
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• pp.26-32
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• 1997

The gate induced drain leakage(GIDL) current under the stress of worse case in -MOSFET's with ultrathin gate oxides has been measured and characterized. The GIDL current was shown that P-MOSFET's of the thicker gate oxide is smaller than that of the thinner gate oxide. It was the results that the this cur-rent is decreased with the increamental stress time at the same devices.It is analyzed that the formation components of GIDL current are both energy band to band tunneling at high gate-drain voltage and energy band to defect tunneling at low drain-gate voltage. The degradations of GIDL current was analyzed the mechanism of major role in the hot carriers trapping in gate oxide by on-state stress.

• 한국전기전자재료학회논문지
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• 제13권11호
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• pp.914-920
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• 2000

When the charge-trap type SONOS(polysilicon-oxide-nitride-oxide-semiconductor) cells are used to flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM(Nonvolatile Semiconductor Memory) cells were fabricated using 0.35 ㎛ standard memory cell embedded logic process including the ONO cell process, based on retrograde twin-well, single-poly, single metal CMOS(Complementary Metal Oxide Semiconductor) process. The thickness of ONO triple-dielectric for the memory cell is tunnel oxide of 24 $\AA$, nitride of 74 $\AA$, blocking oxide of 25 $\AA$, respectively. The program mode(V$\_$g/=7, 8, 9 V, V$\_$s/=V$\_$d/=-3 V, V$\_$b/=floating) and the erase mode(V$\_$g/=-4, -5, -6 V, V$\_$s/=V$\_$d/=floating, V$\_$b/=3 V) by MFN(Modified Fowler-Nordheim) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation(ΔV$\_$th/, S, G$\_$m/) characteristics than channel MFN tunneling operation. Also, the program inhibit conditins of unselected cell for separated source lines NOR-type flash memory application were investigated. we demonstrated that the phenomenon of the program disturb did not occur at source/drain voltage of 1 V∼12 V and gate voltage of -8 V∼4 V.

• E2M - 전기 전자와 첨단 소재
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• 제8권6호
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• pp.727-736
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• 1995

This paper examines the characteristics and physical properties of the scaled MONOS nonvolatile memory device for low programming voltage EEPROM. The capacitor-type MONOS memory devices with the nitride thicknesses ranging from 41.angs. to 600.angs. have been fabricated. As a result, the 5V-programmable MONOS device has been obtained with a 20ms programming time by scaling the nitride thickness to 57.angs. with a tunneling oxide thickness of 19.angs. and a blocking oxide thickness of 20.angs.. Measurement results of the quasi-static C-V curves indicate, after 10$\^$6/ write/erase cycles, that the devices are degraded due to the increase of the silicon-tunneling oxide interface traps. The 10-year retention is impossible for the device with a nitride less than 129.angs.. However, the MONOS memory device with 10-year retentivity has been obtained by increasing the blocking oxide thickness to 47.angs.. Also, the memory traps such as the nitride bulk trap and the blocking oxide-nitride interface trap have been investigated by measuring the maximum flatband voltage shift and analyzing through the best fitting method.

• 한국전기전자재료학회논문지
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• 제22권1호
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• pp.17-21
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• 2009

The electrical characteristics of band-gap engineered tunneling barriers consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were investigated for nonvolatile memory device applications. The band structure of band-gap engineered tunneling barriers was studied and the effectiveness of these tunneling barriers was compared with the conventional tunneling $SiO_2$ barrier. The band-gap engineered tunneling barriers composed of thin $SiO_2$ and $Si_3N_4$ layers showed a lower operation voltage, faster speed and longer retention time than the conventional $SiO_2$ tunnel barrier. The thickness of each $SiO_2$ and $Si_3N_4$ layer was optimized to improve the performance of non-volatile memory.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.156-161
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• 2017

This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

• Journal of information and communication convergence engineering
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• 제5권1호
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• pp.45-49
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• 2007

The analytical transport model in subthreshold regime for double gate MOSFET has been presented to analyze the short channel effects such as subthreshold swing, threshold voltage roll-off and drain induced barrier lowering. The present approach includes the quantum tunneling of carriers through the source-drain barrier. Poisson equation is used for modeling thermionic emission current, and Wentzel-Kramers-Brillouin approximations are applied for modeling quantum tunneling current. This model has been used to investigate the subthreshold operations of double gate MOSFET having the gate length of the nanometer range with ultra thin gate oxide and channel thickness under sub-20nm. Compared with results of two dimensional numerical simulations, the results in this study show good agreements with those for subthreshold swing and threshold voltage roll-off. Note the short channel effects degrade due to quantum tunneling, especially in the gate length of below 10nm, and DGMOSFETs have to be very strictly designed in the regime of below 10nm gate length since quantum tunneling becomes the main transport mechanism in the subthreshold region.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1997년도 추계학술대회 논문집
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• pp.25-29
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• 1997

Capacitor-type MONOS (metal-oxide-nitride-oxide- semiconductor) NVSMs with 23$\AA$ tunneling oxide and 40$\AA$ blocking oxide were fabricated. The thicknesses of nitride layer were 45$\AA$, 91$\AA$ and 223$\AA$, Breakdown characteristics of MONOS devices were measured to investigate the reliability of superthin ONO structure using ramp voltage and constant voltage method. Reducing the nitride thickness will significantly increase the reliablity of MONOS NVSM.

• Journal of Welding and Joining
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• 제33권2호
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• pp.14-17
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• 2015

Cleaning effect is well known mechanism of oxide layer removal in DCEP polarity. It is also known that DCEN has higher heat input efficiency than DCEP in GTAW process. Based on these two renowned arc theories, conventional variable polarity arc for aluminum welding was set up to have minimum DCEP and maximum DCEN duty ratio to achieve the highest heat input efficiency and weldability increase. However, recent several variable polarity GTA research papers reported unexpected result of proportional relationship between DCEP duty ratio and heat input. The authors also observed the same result then suggested combination of tunneling effect and random walk of cathode spot to fill up the gap between experiment and conventional arc theory. In this research, suggested combinational work of tunneling effect and rapid cathode spot changing is applied to another unexpected phenomena of variable polarity aluminum arc welding. From previous research, it is reported that wider oxide removal range, narrower bead width and shallower penetration depth are observed in thin oxide layered aluminum compared to the case of thick oxide. This result was reported for the first time and it was hard to explain the reason at that time therefore the inference by the authors was hardly acceptable. However, the suggested combinational theory successfully explains the result of the previous report in logical way.