• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.382-382
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• 2010

$TaO_2$ thin films as gate dielectrics have been proposed to overcome the problems of tunneling current and degradation mobility in achieving a thin equivalent oxide thickness. An extremely thin $SiO_2$ layer is used in order to separate the carrier in MOSFETchannel from the dielectric field fluctuation caused by phonons in the dielectric which decreases the carrier mobility. The electronic and optical properties influenced the device performance to a great extent. The atomic structure of amorphous and crystalline Tantalum oxide ($TaO_2$) gate dielectrics thin film on Si (100) were grown by utilizing atomic layer deposition method was examined using Ta-K edge x-ray absorption spectroscopy. By using X-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy (REELS) the electronic and optical properties was obtained. In this study, the band gap (3.400.1 eV) and the optical properties of $TaO_2$ thin films were obtained from the experimental inelastic scattering cross section of reflection electron energy loss spectroscopy (REELS) spectra. EXAFS spectra show that the ordered bonding of Ta-Ta for c-$TaO_2$ which is not for c-$TaO_2$ thin film. The optical properties' e.g., index refractive (n), extinction coefficient (k) and dielectric function ($\varepsilon$) were obtained from REELS spectra by using QUEELS-$\varepsilon$(k, $\omega$)-REELS software shows good agreement with other results. The energy-dependent behaviors of reflection, absorption or transparency in $TaO_2$ thin films also have been determined from the optical properties.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2017년도 춘계학술대회
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• pp.688-690
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• 2017

항복전압의 감소는 채널길이 감소에 의하여 발생하는 심각한 단채널 효과이다. 트랜지스터 동작 중에 발생하는 단채널 효과는 트랜지스터의 동작범위를 감소시키는 문제를 발생시킨다. 본 논문에서는 10 nm 이하 채널길이를 갖는 이중게이트 MOSFET에서 채널크기의 변화를 파라미터로 하여 채널도핑에 따른 항복전압의 변화를 고찰하였다. 이를 위하여 해석학적 전위분포에 의한 열방사 전류와 터널링 전류를 구하고 두 성분의 합으로 구성된 드레인 전류가 $10{\mu}A$가 될 때, 드레인 전압을 항복전압으로 정의하였다. 결과적으로 채널 도핑농도가 증가할수록 항복전압은 크게 증가하였다. 채널길이가 감소하면서 항복전압이 크게 감소하였으며 이를 해결하기 위하여 실리콘 두께 및 산화막 두께를 매우 작게 유지하여야만 한다는 것을 알 수 있었다. 특히 터널링 전류의 구성비가 증가할수록 항복전압이 증가하는 것을 관찰하였다.

• 한국재료학회지
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• 제34권4호
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• pp.202-207
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• 2024

In this study, we undertook detailed experiments to increase hydrogen production efficiency by optimizing the thickness of titanium dioxide (TiO₂) thin films. TiO₂ films were deposited on p-type silicon (Si) wafers using atomic layer deposition (ALD) technology. The main goal was to identify the optimal thickness of TiO₂ film that would maximize hydrogen production efficiency while maintaining stable operating conditions. The photoelectrochemical (PEC) properties of the TiO₂ films of different thicknesses were evaluated using open circuit potential (OCP) and linear sweep voltammetry (LSV) analysis. These techniques play a pivotal role in evaluating the electrochemical behavior and photoactivity of semiconductor materials in PEC systems. Our results showed photovoltage tended to improve with increasing thickness of TiO₂ deposition. However, this improvement was observed to plateau and eventually decline when the thickness exceeded 1.5 nm, showing a correlation between charge transfer efficiency and tunneling. On the other hand, LSV analysis showed bare Si had the greatest efficiency, and that the deposition of TiO₂ caused a positive change in the formation of photovoltage, but was not optimal. We show that oxide tunneling-capable TiO₂ film thicknesses of 1~2 nm have the potential to improve the efficiency of PEC hydrogen production systems. This study not only reveals the complex relationship between film thickness and PEC performance, but also enabled greater efficiency and set a benchmark for future research aimed at developing sustainable hydrogen production technologies.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.167-173
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• 2017

In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.

• 마이크로전자및패키징학회지
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• 제24권3호
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• pp.7-11
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• 2017

본 논문은 3차원 낸드 플래쉬 기억 소자에 적용을 위해 소노스(SONOS) 형태로 기억 저장 절연막을 채용하고 채널로 폴리실리콘을 사용한 박막형 트랜지스터에 대해 연구하였다. 셀의 source/drain에는 불순물을 주입 하지 않았고, 셀 양 끝단에는 선택 트랜지스터를 배치하였다. 셀의 채널과 선택 트랜지스터의 source/drain 불순물 농도 변화에 대한 평가를 진행하여 공정 최적화를 하였다. 선택 트랜지스터의 농도 증가 시 채널 전류의 상승 및 삭제특성이 개선됨을 확인 하였는데 이는 GIDL에 의한 홀 생성이 증가하였기 때문이다. 최적화된 공정 변수에 대해 삭제와 쓰기 후 문턱전압의 프로그램 윈도우는 대략 2.5V를 얻었다. 터널 산화막 공정 온도에 대한 평가 결과 온도 증가 시 swing 및 신뢰성 항목인 bake 결과가 개선됨을 확인하였다.

• 한국전기전자재료학회논문지
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• 제17권8호
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• pp.875-881
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• 2004

Fundamental results obtained from an atomic force microscope (AFM) chemically-induced direct nano-lithography process are presented, which is regarded as a simple method for fabrication nm-scale devices such as superconducting flux flow transistors (SFFTs) and single electron tunneling transistors (SETs). Si cantilevers with Pt coating and with 30 nm thick TiO coating were used as conducting AFM tips in this study. We observed the surfaces of superconducting strip lines modified by AFM anodization' process. First, superconducting strip lines with scan size 2 ${\mu}{\textrm}{m}$${\times}$2 ${\mu}{\textrm}{m}$ have been anodized by AFM technology. The surface roughness was increased with the number of AFM scanning, The roughness variation was higher in case of the AFM tip with a positive voltage than with a negative voltage in respect of the strip surface. Second, we have patterned nm-scale oxide lines on ${YBa}-2{Cu}_3{O}_{7-x}$ superconducting microstrip surfaces by AFM conductive cantilever with a negative bias voltage. The ${YBa}-2{Cu}_3{O}_{7-x}$ oxide lines could be patterned by anodization technique. This research showed that the critical characteristics of superconducting thin films were be controlled by AFM anodization process technique. The AFM technique was expected to be used as a promising anodization technique for fabrication of an SFFT with nano-channel.

• 센서학회지
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• 제7권2호
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• pp.97-102
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• 1998

PPV(poly(p-phenylenevinylene))를 발광체로 이용한 유기 박막 EL 소자를 다양한 구조와 조건으로 제작하였으며, 그 전기-광학적 특성을 평가하였다. 제작된 EL 소자는 단층구조(ITO(indium tin oxide)PPV/Mg), 이층구조 (ITO/PVK(poly(N-vinylcarbazole))/PPV)Mg와 ITO/PPV/Polymer matrix+PBD/Mg) 그리고 삼층구조 (ITO/PVK/PPV/PS(polystyrene)+PBD(butyl-2-(4-biphenyl)-5-(4-tert-butylphenyl-1,3,4-oxadiazole))/Mg)를 가지며, 그들의 전기광학적 특성을 상호 비교하였다. 이층구조(ITO/PPV)Polymer matrix+PBD/Mg)에서는 PMMA (poly(methyl methacrylate)), PC(polycarbonate) PS 와 MCH(side chain liquid crystalline homopolymer)를 고분자 메트릭스로 사용하였으며, 특히, PS 고분자 메트 릭스를 전자수송층으로 사용하는 경우에 전자수송제인 PBD의 농도에 따른 발광휘도 특성을 구하였다. 제작된 소자의 인가전압에 따른 전류, 휘도특성을 분석한 결과 터널링효과를 나타내었고 안정된 발광특성을 가진다는 것을 알 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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• pp.35-38
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• 2002

In this paper, the characteristics of channel hot electron (CHE) injection for the write operation in a NOR-type SONOS flash memory with common source line were investigated. The thicknesses of he tunnel oxide, the memory nitride， and the blocking oxide layers for the gate insulator of the fabricated SONOS devices were $34{\AA}$, $73{\AA}$, and $34{\AA}$, respectively. The SONOS devices compared to floating gate devices have many advantages, which are a simpler cell structure, compatibility with conventional logic CMOS process and a superior scalability. For these reasons, the introduction of SONOS device has stimulated. In the conventional SONOS devices, Modified Folwer-Nordheim (MFN) tunneling and CHE injection for writing require high voltages, which are typically in the range of 9 V to 15 V. However CHE injection in our devices was achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The memory window of about 3.2 V and the write speed of $100{\mu}s$ were obtained. Also, the disturbance and drain turn-on leakage during CHE injection were not affected in the SONOS array. These results show that CHE injection can be achieved with a low voltage and single power supply, and applied for the high speed program of the SONOS memory devices.

• 한국정보통신학회논문지
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• 제21권8호
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• pp.1465-1470
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• 2017

기존의 MOSFET에서는 반전층보다 항상 실리콘 두께가 크기 때문에 드레인유도 장벽감소가 실리콘 두께에 관계없이 산화막 두께 및 채널길이의 함수로 표현되었다. 그러나 10 nm 이하 저도핑 이중게이트 구조에서는 실리콘 두께 전체가 공핍층이 형성되기 때문에 기존의 SPICE 모델을 사용할 수 없게 되었다. 그러므로 이중게이트 MOSFET에 대한 새로운 SPICE 용 드레인유도 장벽감소 모델을 제시하고자 한다. 이를 분석하기 위하여 전위분포와 WKB 근사를 이용하여 열방사 및 터널링 전류를 구하였다. 결과적으로 드레인유도 장벽감소는 상하단 산화막 두께의 합 그리고 실리콘 두께의 2승에 비례하며 채널길이의 3승에 반비례한다는 것을 알 수 있었다. 특히 SPICE 파라미터인 정적 궤환계수가 1과 2사이에서 사용할 수 있어 합당한 파라미터로써 사용할 수 있었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1268-1270
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• 1993

In this study, the characteristics of Si-$SiO_2$ interface and its degradation in short channel SONOSFET nonvolatile memory devices, fabricated by 1Mbit CMOS process($1.2{\mu}m$ design rule), with $65{\AA}$ blocking oxide layer, $205{\AA}$ nitride layer, and $30{\AA}$ tunneling oxide layer on the silicon wafer were investigated using the charge pumping method. For investigating the Si-$SiO_2$ interface characteristics before and after write/erase cycling, charge pumping current characteristics with frequencies, write/erase cycles, as a parameters, were measured. As a result, average Si-$SiO_2$ interface trap density and mean value of capture cross section were determined to be $1.203{\times}10^{11}cm^{-2}eV^{-1}\;and\;2.091{\times}10^{16}cm^2$ before write/erase cycling, respectively. After cycling, when the write/erase cycles are $10^4$, average $Si-SiO_2$ interface trap density was $1.901{\times}10^{11}cm^{-2}eV^{-1}$. Incresing write/erase cycles beyond about $10^4$, Si-$SiO_2$ interface characteristics with write/erase cycles was increased logarithmically.