• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.382-382
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• 2010

$TaO_2$ thin films as gate dielectrics have been proposed to overcome the problems of tunneling current and degradation mobility in achieving a thin equivalent oxide thickness. An extremely thin $SiO_2$ layer is used in order to separate the carrier in MOSFETchannel from the dielectric field fluctuation caused by phonons in the dielectric which decreases the carrier mobility. The electronic and optical properties influenced the device performance to a great extent. The atomic structure of amorphous and crystalline Tantalum oxide ($TaO_2$) gate dielectrics thin film on Si (100) were grown by utilizing atomic layer deposition method was examined using Ta-K edge x-ray absorption spectroscopy. By using X-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy (REELS) the electronic and optical properties was obtained. In this study, the band gap (3.400.1 eV) and the optical properties of $TaO_2$ thin films were obtained from the experimental inelastic scattering cross section of reflection electron energy loss spectroscopy (REELS) spectra. EXAFS spectra show that the ordered bonding of Ta-Ta for c-$TaO_2$ which is not for c-$TaO_2$ thin film. The optical properties' e.g., index refractive (n), extinction coefficient (k) and dielectric function ($\varepsilon$) were obtained from REELS spectra by using QUEELS-$\varepsilon$(k, $\omega$)-REELS software shows good agreement with other results. The energy-dependent behaviors of reflection, absorption or transparency in $TaO_2$ thin films also have been determined from the optical properties.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.688-690
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• 2017

Reduction of breakdown voltage is serious short channel effect (SCE) by shrink of channel length. The SCE occurred in on-state transistor raises limitation of operation range of transistor. The deviation of breakdown voltage for doping concentration is investigated with structural parameters of sub-10 nm double gate (DG) MOSFET in this paper. To analyze this, thermionic and tunneling current are derived from analytical potential distribution, and breakdown voltage is defined as drain voltage when the sum of two currents is $10{\mu}A$. As a result, breakdown voltage increases with increase of doping concentration. Breakdown voltage decreases by reduction of channel length. In order to solve this problem, it is found that silicon and oxide thicknesses should be kept very small. In particular, as contributions of tunneling current increases, breakdown voltage increases.

• Korean Journal of Materials Research
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• v.34 no.4
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• pp.202-207
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• 2024

In this study, we undertook detailed experiments to increase hydrogen production efficiency by optimizing the thickness of titanium dioxide (TiO₂) thin films. TiO₂ films were deposited on p-type silicon (Si) wafers using atomic layer deposition (ALD) technology. The main goal was to identify the optimal thickness of TiO₂ film that would maximize hydrogen production efficiency while maintaining stable operating conditions. The photoelectrochemical (PEC) properties of the TiO₂ films of different thicknesses were evaluated using open circuit potential (OCP) and linear sweep voltammetry (LSV) analysis. These techniques play a pivotal role in evaluating the electrochemical behavior and photoactivity of semiconductor materials in PEC systems. Our results showed photovoltage tended to improve with increasing thickness of TiO₂ deposition. However, this improvement was observed to plateau and eventually decline when the thickness exceeded 1.5 nm, showing a correlation between charge transfer efficiency and tunneling. On the other hand, LSV analysis showed bare Si had the greatest efficiency, and that the deposition of TiO₂ caused a positive change in the formation of photovoltage, but was not optimal. We show that oxide tunneling-capable TiO₂ film thicknesses of 1~2 nm have the potential to improve the efficiency of PEC hydrogen production systems. This study not only reveals the complex relationship between film thickness and PEC performance, but also enabled greater efficiency and set a benchmark for future research aimed at developing sustainable hydrogen production technologies.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.167-173
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• 2017

In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.7-11
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• 2017

In this paper, we have studied the characteristics of NAND Flash memory in SONOS Poly-Si Thin Film Transistor (Poly-Si TFT) device. Source/drain junctions(S/D) of cells were not implanted and selective transistors were located in the end of cells. We found the optimum conditions of process by means of the estimation for the doping concentration of channel and source/drain of selective transistor. As the doping concentration was increased, the channel current was increased and the characteristic of erase was improved. It was believed that the improvement of erase characteristic was probably due to the higher channel potential induced by GIDL current at the abrupt junction. In the condition of process optimum, program windows of threshold voltages were about 2.5V after writing and erasing. In addition, it was obtained that the swing value of poly Si TFT and the reliability by bake were enhanced by increasing process temperature of tunnel oxide.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.8
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• pp.875-881
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• 2004

Fundamental results obtained from an atomic force microscope (AFM) chemically-induced direct nano-lithography process are presented, which is regarded as a simple method for fabrication nm-scale devices such as superconducting flux flow transistors (SFFTs) and single electron tunneling transistors (SETs). Si cantilevers with Pt coating and with 30 nm thick TiO coating were used as conducting AFM tips in this study. We observed the surfaces of superconducting strip lines modified by AFM anodization' process. First, superconducting strip lines with scan size 2 ${\mu}{\textrm}{m}$${\times}$2 ${\mu}{\textrm}{m}$ have been anodized by AFM technology. The surface roughness was increased with the number of AFM scanning, The roughness variation was higher in case of the AFM tip with a positive voltage than with a negative voltage in respect of the strip surface. Second, we have patterned nm-scale oxide lines on ${YBa}-2{Cu}_3{O}_{7-x}$ superconducting microstrip surfaces by AFM conductive cantilever with a negative bias voltage. The ${YBa}-2{Cu}_3{O}_{7-x}$ oxide lines could be patterned by anodization technique. This research showed that the critical characteristics of superconducting thin films were be controlled by AFM anodization process technique. The AFM technique was expected to be used as a promising anodization technique for fabrication of an SFFT with nano-channel.

• Journal of Sensor Science and Technology
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• v.7 no.2
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• pp.97-102
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• 1998

Organic thin film EL devices using PPV(poly (p-phenylenevinylene)) as emitter were fabricated on various conditions and structures, their electro-optical properties were estimated. Fabricated EL devices had structures of single layer(ITO(indium tin oxide)/PPV/Mg), double layer(ITO/PVK(poly(N-vinylcarbazole))/PPV/Mg and ITO/PPV/Polymer matrix + PBD/Mg) and three layer (ITO/PVK/PPV/PS(polystyrene)+PBD(butyl-2-(4-bipheny])-5-(4-tert-butylphenyl-1,3,4-oxadiazole))/Mg), their electro-optical characteristics were compared with each other. In structure of double layer (ITO/PPV /Polymer matrix + PBD/Mg), the used polymer-matrices were PMMA(poly(methyl methacrylate), PC(polycarbonate), PS and MCH(side chain liquid crystalline homopolymer). When PS as a hole transport layer was used, the luminance characteristics on concentration of PBD was obtained. In results, current-voltage-luminance curves of fabricated devices had characteristics of tunneling effect and the device showed a stable light emitting.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.35-38
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• 2002

In this paper, the characteristics of channel hot electron (CHE) injection for the write operation in a NOR-type SONOS flash memory with common source line were investigated. The thicknesses of he tunnel oxide, the memory nitride， and the blocking oxide layers for the gate insulator of the fabricated SONOS devices were $34{\AA}$, $73{\AA}$, and $34{\AA}$, respectively. The SONOS devices compared to floating gate devices have many advantages, which are a simpler cell structure, compatibility with conventional logic CMOS process and a superior scalability. For these reasons, the introduction of SONOS device has stimulated. In the conventional SONOS devices, Modified Folwer-Nordheim (MFN) tunneling and CHE injection for writing require high voltages, which are typically in the range of 9 V to 15 V. However CHE injection in our devices was achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The memory window of about 3.2 V and the write speed of $100{\mu}s$ were obtained. Also, the disturbance and drain turn-on leakage during CHE injection were not affected in the SONOS array. These results show that CHE injection can be achieved with a low voltage and single power supply, and applied for the high speed program of the SONOS memory devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.8
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• pp.1465-1470
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• 2017

In conventional MOSFETs, the silicon thickness is always larger than inversion layer, so that the drain induced barrier lowering (DIBL) is expressed as a function of oxide thickness and channel length regardless of silicon thickness. However, since the silicon thickness is fully depleted in the sub-10 nm low doped double gate (DG) MOSFET, the conventional SPICE model for DIBL is no longer available. Therefore, we propose a novel DIBL SPICE model for DGMOSFETs. In order to analyze this, a thermionic emission and the tunneling current was obtained by the potential and WKB approximation. As a result, it was found that the DIBL was proportional to the sum of the top and bottom oxide thicknesses and the square of the silicon thickness, and inversely proportional to the third power of the channel length. Particularly, static feedback coefficient of SPICE parameter can be used between 1 and 2 as a reasonable parameter.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1268-1270
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• 1993

In this study, the characteristics of Si-$SiO_2$ interface and its degradation in short channel SONOSFET nonvolatile memory devices, fabricated by 1Mbit CMOS process($1.2{\mu}m$ design rule), with $65{\AA}$ blocking oxide layer, $205{\AA}$ nitride layer, and $30{\AA}$ tunneling oxide layer on the silicon wafer were investigated using the charge pumping method. For investigating the Si-$SiO_2$ interface characteristics before and after write/erase cycling, charge pumping current characteristics with frequencies, write/erase cycles, as a parameters, were measured. As a result, average Si-$SiO_2$ interface trap density and mean value of capture cross section were determined to be $1.203{\times}10^{11}cm^{-2}eV^{-1}\;and\;2.091{\times}10^{16}cm^2$ before write/erase cycling, respectively. After cycling, when the write/erase cycles are $10^4$, average $Si-SiO_2$ interface trap density was $1.901{\times}10^{11}cm^{-2}eV^{-1}$. Incresing write/erase cycles beyond about $10^4$, Si-$SiO_2$ interface characteristics with write/erase cycles was increased logarithmically.