• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.2
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• pp.103-110
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• 2001

Gate oxide scaling for sub-l00nm CMOS devices has been studied. Issues on the gate oxide scaling are reviewed, which are boron penetration, reliability, and direct tunneling leakage currents. Reliability of Sub-2.0nm oxides and the device performance degradation due to boron penetration are investigated. Especially, the effect of gate leakage currents on the transistor characteristics is studied. As a result, it is proposed that thinner oxides than previous expectations may be usable as scaling proceeds. Based on the gate oxide thickness optimization process we have established, high performance CMOS transistors of $L_{gate}=70nm$ and $T_{ox}=1.4nm$ were fabricated, which showed excellent current drives of $860\mu\textrm{A}/\mu\textrm{m}$ (NMOS) and $350\mu\textrm{A}/\mu\textrm{m}$ (PMOS) at $I_{off}=10\mu\textrm{A}/\mu\textrm{m}$ and $V_dd=1.2V$, and CV/I of 1.60ps (NMOS) and 3.32ps(PMOS).

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.339-339
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• 2010

The metallic nanoparticles (Pt, Au, Ag. Cu, etc.) supported on ceria-titania mixed oxide exhibit a high catalytic activity for the water gas shift reaction ($H_2O\;+\;CO\;{\leftrightarrow}\;H_2\;+\;CO_2$) and the CO oxidation ($O_2\;+\;2CO\;{\leftrightarrow}\;2CO_2$). It has been speculated that the high catalytic activity is related to the easy exchange of the oxidation states of ceria ($Ce^{3+}$ and $Ce^{4+}$) on titania, but very little is known about the ceria titanium interaction, the growth mode of metal on ceria titania complex, and the reaction mechanism. In this work, the growth of $CeO_x$ and Au/$CeO_x$ on rutile $TiO_2$(110) have been investigated by Scanning Tunneling Microscopy (STM), Photoelectron Spectroscopy (PES), and DFT calculation. In the $CeO_x/TiO_2$(110) systems, the titania substrate imposes on the ceria nanoparticles non-typical coordination modes, favoring a $Ce^{3+}$ oxidation state and enhancing their chemical activity. The deposition of metal on a $CeO_x/TiO_2$(110) substrate generates much smaller nanoparticles with an extremely high activity. We proposed a mechanism that there is a strong coupling of the chemical properties of the admetal and the mixed-metal oxide: The adsorption and dissociation of water probably take place on the oxide, CO adsorbs on the admetal nanoparticles, and all subsequent reaction steps occur at the oxide-admetal interface.

• Journal of the Korean Magnetics Society
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• v.22 no.4
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• pp.147-156
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• 2012

Recently, there have been considerable interests in various thin film growth techniques with atomically controllable thickness. Among them, atomically controlled pulsed laser deposition (PLD) technique is quite popular. We have developed advanced thin film growth technique using PLD and Reflection high energy electron diffraction (RHEED). Using the technique, the growth of oxide thin films with the precisely controllable thickness has been demonstrated. In addition, our technique can be applied to high quality thin film growth with minimal defect and bulk chemical composition. In this paper, our recent progresses as well as the current research trend on oxide thin films will be summarized.

• Transactions on Electrical and Electronic Materials
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• v.18 no.4
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• pp.225-228
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• 2017

In this study, zinc tin oxide (ZTO) films were prepared on indium tin oxide (ITO) glasses and annealed at different temperatures under vacuum to investigate the correlation between the Ohmic/Schottky contacts, electrical properties, and bonding structures with respect to the annealing temperatures. The ZTO film annealed at $150^{\circ}C$ exhibited an amorphous structure because of the electron-hole recombination effect, and the current of the ZTO film annealed at $150^{\circ}C$ was less than that of the other films because of the potential barrier effect at the Schottky contact. The drift current as charge carriers was similar to the leakage current in a transparent thin-film device, but the diffusion current related to the Schottky barrier leads to the decrease in the leakage current. The direction of the diffusion current was opposite to that of the drift current resulting in a two-fold enhancement of the cut-off effect of leakage drift current due to the diffusion current, and improved performance of the device with the Schottky barrier. Hence, the thin film with an amorphous structure easily becomes a Schottky contact.

• Proceedings of the Materials Research Society of Korea Conference
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• 1999.11a
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• pp.30-30
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• 1999

No Abstract.see full/text

• Proceeding of EDISON Challenge
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• 2015.03a
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• pp.350-353
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• 2015

최근 에너지 효율과 소형화측면에서 한계를 보이는 Metal-Oxide-Semiconductor Field-Effect Transistor(MOSFET)을 대체할 수 있는 소자로 Tunneling FET(TFET)이 주목받고 있다. 본 논문에서는 탄소나노튜브(Carbon Nanotube, CNT) TFET을 시뮬레이션하여 전자회로의 기본 단위인 인버터(Inverter)를 설계한다. 설계한 인버터의 성능을 CNT-MOSFET 인버터와 비교하여 저전력 디지털 회로로써의 가능성을 확인한다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.4
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• pp.541-546
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• 1990

The current conduction and dielectric breakdown properties of oxide grown on phosphorous-doped polysilicon have been investigated by means of the ramped I-V measurements. The effective barrier heights of polyoxide grown by different silicon deposition and oxidation conditions were calculated from the Fowler-Nordheim tunneling characteristic. The average critical fields were also obtained for each film. From the results, the high temperature oxided polyoxide grown on amorphous silicon film shows superior electrical characteristics comparing to the other films.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.1-8
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• 2004

Experimental results are presented for gate oxide degradation, such as SILC and soft breakdown, and its effect on device parameters under negative and positive bias stress conditions using n-MOSFET's with 3 nm gate oxide. The degradation mechanisms are highly dependent on stress conditions. For negative gate voltage, both interface and oxide bulk traps are found to dominate the reliability of gate oxide. However, for positive gate voltage, the degradation becomes dominated mainly by interface trap. It was also found the trap generation in the gate oxide film is related to the breakage of Si-H bonds through the deuterium anneal and additional hydrogen anneal experiments. Statistical parameter variations as well as the “OFF” leakage current depend on both electron- and hole-trapping. Our results therefore show that Si or O bond breakage by tunneling electron and hole can be another origin of the investigated gate oxide degradation. This plausible physical explanation is based on both Anode-Hole Injection and Hydrogen-Released model.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.40-43
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• 2000

The electrons and holes trapped in the tunneling oxide and interface-states generated in the Si/SiO$_2$ interface during program/erase (P/E) operations are known to cause reliability problems which can deteriorate the cell performance and cause the V$_{th}$ window close. This deterioration is caused by the accumulation of electrons and holes trapped in the oxide near the drain and source side after each P/E cycle. we propose three new erase schemes to improve the cell's endurance characteristics: (1)adding a Reverse soft program cycle after the source erase operation, (2)adding a detrapping cycle after the source erase operation, (3)adding a convergence cycle after the source erase operation. (3) is the most effective performance among the three erase schemes have been implemented and shown to significantly reduce the V$_{th}$ window close problem. And we are able to design the reliable periperal circuit of flash memory by using the (3).(3).

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.1
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• pp.13-18
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• 1999

The trap density by the stress bias in silicon oxides with different thicknesses has been investigated. The trap density by stress bias was shown to be composed of on time current and off time current. The on time trap density was composed of dc current. The off time trap density was caused by the tunneling charging and discharging of the trap in the interfaces. The on time trap density was used to estimate to the limitations on oxide thicknesses. The off time trap density was used to estimate the data retention in nonvolatile memory devices.