• Geomechanics and Engineering
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• 제19권1호
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• pp.93-104
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• 2019

Anomalies and/or fractured grounds not detected by the surface geophysical and geological survey performed during design stage may cause significant problems during tunnel excavation. Many studies on prediction methods of the ground condition ahead of the tunnel face have been conducted and applied in tunneling construction sites, such as tunnel seismic profiling and probe drilling. However, most such applications have focused on the drill and blast tunneling method. Few studies have been conducted for mechanized tunneling because of the limitation in the available space to perform prediction tests. This study aims to predict the ground condition ahead of the tunnel face in TBM tunneling by using an electrical resistivity tomography survey. It compared the characteristics of each electrode array and performed an investigation on in-situ tunnel boring machine TBM construction site environments. Numerical simulations for each electrode array were performed, to determine the proper electrode array to predict anomalies ahead of the tunnel face. The results showed that the modified dipole-dipole array is, compared to other arrays, the best for predicting the location and condition of an anomaly. As the borehole becomes longer, the measured data increase accordingly. Therefore, longer boreholes allow a more accurate prediction of the location and status of anomalies and complex grounds.

• 한국컴퓨터정보학회논문지
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• 제17권11호
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• pp.73-81
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• 2012

본 논문에서는 애드 혹 네트워크의 노드 위치 정보와 홉 수를 이용하여 캡슐화 웜홀 공격과 터널링 웜홀 공격을 탐지하는 ETWAD(Encapsulation and Tunneling Wormhole Attack Detection) 기법을 설계하였다. ETWAD 탐지 기법은 애드 혹 네트워크 내의 노드 ID와 그룹 키로 노드의 신분을 확인할 수 있는 GAK(Group Authentication Key)를 생성하여 RREQ와 RREP에 추가하여 애드 혹 네트워크의 구성원임으로 인증할 수 있도록 설계하였다. 또한, ETWAD 탐지 기법은 RREP 메시지 내의 홉 수를 카운트하고, 근원지 노드 S와 목적지 노드 D의 거리를 계산하여 임계치와 홉 수를 이용하여 캡슐화 웜홀 공격, 터널링 공격을 탐지하는 GeoWAD 알고리즘을 설계하였다. 그 결과, 평균 웜홀 공격 탐지율이 91%, 평균 FPR이 4.4%로 평가되므로 ETWAD 탐지 기법은 웜홀 공격 탐지율과 웜홀 공격 탐지의 신뢰성을 향상시켰다고 볼 수 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.245-251
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• 2013

The effect of band-to-band tunneling (BTBT) leads to an obvious increase of the leakage current of junctionless (JL) transistors in the OFF state. In this paper, we propose an effective method to decline the influence of BTBT with the example of n-type double gate (DG) JL metal-oxide-semiconductor field-effect transistors (MOSFETs). The leakage current is restrained by changing the geometrical shape and the physical dimension of the gate of the device. The optimal design of the JL MOSFET is indicated for reducing the effect of BTBT through simulation and analysis.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.172-178
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• 2016

In this paper, we propose a sub-10 nm Ge/GaAs heterojunction-based tunneling field-effect transistor (TFET) with vertical band-to-band tunneling (BBT) operation for ultra-low-power (LP) applications. We design a stack structure that is based on the Ge/GaAs heterojunction to realize the vertical BBT operation. The use of vertical BBT operations in devices results in excellent subthreshold characteristics with a reduction in the drain-induced barrier thinning (DIBT) phenomenon. The proposed device with a channel length ($L_{ch}$) of 5 nm exhibits outstanding LP performance with a subthreshold swing (S) of 29.1 mV/dec and an off-state current ($I_{off}$) of $1.12{\times}10^{-11}A/{\mu}m$. In addition, the use of the highk spacer dielectric $HfO_2$ improves the on-state current ($I_{on}$) with an intrinsic delay time (${\tau}$) because of a higher fringing field. We demonstrate a sub-10 nm LP switching device that realizes a good S and lower $I_{off}$ at a lower supply voltage ($V_{DD}$) of 0.2 V.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.630-634
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• 2016

We report the computer aided design results for a GaSb/InAs broken-gap gate all around nanowire tunneling FET (TFET). In designing, the semi-empirical tight-binding (TB) method using $sp3d5s^*$ is used as band structure model to produce the bulk properties. The calculated band structure is cooperated with open boundary conditions (OBCs) and a three-dimensional $Schr{\ddot{o}}dinger$-Poisson solver to execute quantum transport simulators. We find an device configuration for the operation voltage of 0.3 V which exhibit desired low sub-threshold swing (< 60 mV/dec) by adopting receded gate configuration while maintaining the high current characteristic ($I_{ON}$ > $100 {\mu}A/{\mu}m$) that broken-gap TFETs normally have.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권3호
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• pp.139-144
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• 2003

We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.

• 대한기계학회논문집
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• 제17권7호
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• pp.1731-1739
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• 1993

An application of Scanning Tunneling Microscopy(STM) is investigated for the measurement of 3-dimensional profiles of the macro-machined patterns of which critical dimensions lie in the range of submicrometers. Special emphasis of this investigation is given to extending the measuring ranges of STM upto the order of several micrometers while maintaining superb nanometer measuring resolution. This is accomplished by correcting hysteresis effects of piezoelectric actuators by using non-linear compensation models. Detailed aspects of design and control of a prototype measurement system are described with some actual measuring examples in which fine It patterns can successfully be traced with a resolution of 1 nanometer over a surface range of $4{\times}2$ micrometers.

• 한국지반공학회:학술대회논문집
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• 한국지반공학회 2010년도 추계 학술발표회
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• pp.1314-1321
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• 2010

The west express way which links south west area of the central city of Seoul has been notorious for extremely heavy traffics since its first opening in 1991(i.e. the average vehicle speed is less than 25km/h, a daily traffic is 112,000 and among them, more than 94% of the vehicles are the light vehicles). The city government recently initiated a new BTO(Build-Transfer-Operate) project as an alternative in releasing heavy traffic and a high construction cost. The proposed underground express road is the first double-level tunnel (i.e. a total length of road is 10,91km and the tunnel is 9.308km long) ever built in South Korea, while such tunnel system is not new worldwide as such A86 East tunnel in France, SMART tunnel in Malaysia, and Fuxing tunnel in China. This paper discusses major design issues regarding the internal structures such as deck slab, and secondary liner.

• Geomechanics and Engineering
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• 제17권3호
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• pp.237-245
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• 2019

In deep mixed rock strata, a double shield TBM (DS-TBM) is easy to be entrapped by a large force during tunneling. In order to reduce the probability of the entrapment, we need to investigate a favorable driving direction, either driving with or against dip, which mainly associates with the angle between the tunneling axis and strike, ${\theta}$, as well as the dip angle of rock strata, ${\alpha}$. We, therefore, establish a 3DEC model to show the changes of displacements and contact forces in mixed rock strata through LDP (longitudinal displacement profile) and LFP (longitudinal contact force profile) curves at four characteristic points on the surrounding rock. This is followed by a series of numerical models to investigate the favorable driving direction. The computational results indicate driving with dip is the favorable tunneling direction to reduce the probability of DS-TBM entrapment, irrespective of ${\theta}$ and ${\alpha}$, which is not in full agreement with the guidelines proposed in RMR. From the favorable driving direction (i.e., driving with dip), the smallest contact force is found when ${\theta}$ is equal to $90^{\circ}$. The present study is therefore beneficial for route selection and construction design in TBM tunneling.

• 한국정보통신학회논문지
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• 제21권5호
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• pp.869-875
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• 2017

본 연구에서는 TCAD 시뮬레이션을 이용하여 4가지 터널링 전계효과 트랜지스터(Tunnel Field-Effect Transistors; TFETs) 구조에 따른 특성을 조사하였다. 단일게이트 TFET(SG-TFET), 이중게이트 TFET(DG-TFET), L-shaped TFET(L-TFET), Pocket-TFET(P-TFET)의 4가지 TFET를 유전율과 채널 길이를 변화함에 따라서 드레인 전류-게이트전압 특성을 시뮬레이션해서 문턱전압이하 스윙(Subthreshold Swing; SS)과 구동 전류(On-current)면에서 비교하였다. 고유전율을 가지며 라인 터널링을 이용하는 L-TFET 구조와 P-TFET 구조가 포인트 터널링을 이용하는 SG-TFET와 DG-TFET보다 구동전류면에서 10배 이상 증가하였고, SS면에서 20 mV/dec이상 감소하였다. 특히, 고유전율을 가진 P-TFET의 주 전류 메카니즘이 포인트 터널링에서 라인터널링으로 변화하는 험프현상이 사라지면서 SS가 매우 향상되는 것을 보였다. 4가지 TFET 구조의 분석을 통해 포인트터널링을 줄이고 라인터널링을 강조하는 새로운 TFET 구조의 가이드 라인을 제시한다.