• 한국자동차공학회논문집
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• 제5권2호
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• pp.69-79
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• 1997

This paper deals with the measurement and analysis on the scavenging performance of the oppet-valve type two-stroke engine with different shroud system. The scavenging flow characteristics is investigated by flow visualization under steady condition, in which a dye is introduced into single-cycle method using the difference of specific gravity between two working fluids is used to evaluate the scavenging efficiency and the trapping efficiency. The 90° shroud system was found to be the highest efficiency system through both flow visualization and single-cycle test, as well as the shroud system to generally be efficient for reducing a short-circuiting flow during scavenging process in a two-stoke engine.

• E2M - 전기 전자와 첨단 소재
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• 제10권1호
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• pp.26-32
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• 1997

The gate induced drain leakage(GIDL) current under the stress of worse case in -MOSFET's with ultrathin gate oxides has been measured and characterized. The GIDL current was shown that P-MOSFET's of the thicker gate oxide is smaller than that of the thinner gate oxide. It was the results that the this cur-rent is decreased with the increamental stress time at the same devices.It is analyzed that the formation components of GIDL current are both energy band to band tunneling at high gate-drain voltage and energy band to defect tunneling at low drain-gate voltage. The degradations of GIDL current was analyzed the mechanism of major role in the hot carriers trapping in gate oxide by on-state stress.

• 한국전기전자재료학회논문지
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• 제27권10호
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• pp.648-652
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• 2014

We have investigated the effect of electrical properties of amorphous InGaZnO thin film transistors (a-IGZO TFTs) by post thermal annealing in $O_2$ ambient. The post-annealed in $O_2$ ambient a-IGZOTFT is found to be more stable to be used for oxide-based TFT devices, and has better performance, such as the on/off current ratios, sub-threshold voltage gate swing, and, as well as reasonable threshold voltage, than others do. The interface trap density is controlled to achieve the optimum value of TFT transfer and output characteristics. The device performance is significantly affected by adjusting the annealing condition. This effect is closely related with the modulation annealing method by reducing the localized trapping carriers and defect centers at the interface or in the channel layer.

• Journal of Welding and Joining
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• 제24권3호
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• pp.42-48
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• 2006

Since the voids occur at the CD stud welds, the mechanism of void formation and void reduction method are investigated in this work. It is speculated that the voids are formed because of high short-circuit current above 1000A. When the simple flow model is used to estimate the void trapping condition, the most voids are trapped at the weld mainly due to fast cooling rate of the CD stud weld. Since it is almost impossible to remove the voids completely, a method is proposed to reduce the void by decreasing the short-circuit current at the end of the arcing time. The experimental results show that the void is reduced by decreasing the short-circuit current to 1000A.

• Bulletin of the Korean Chemical Society
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• 제15권12호
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• pp.1103-1107
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• 1994

Interaction of triethylsilane and diphenylsilane ($Ph_2$$SiH_2$, $Ph_2$$SiD_2$) with the surfaces of rhodium has been examined by trapping the reaction intermediates with 2,3-dimethyl-l,3-butadiene. 1,4-Hydrosilylation of the diene is predominantly observed to occur under mild condition over the rhodium catalyst. It is inferred from the product analyses that silylene and silyl radicals bonded to rhodium surfaces are the intermediates for addition of silylene to the diene, and for 1,4-hydrosilylation, respectively.

• 한국지진공학회:학술대회논문집
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• 한국지진공학회 2000년도 추계 학술발표회 논문집 Proceedings of EESK Conference-Fall 2000
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• pp.81-88
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• 2000

The elastic wave equation is solved using the finite-difference method in 3D space to simulate the seismic wave propagation. It is based on the velocity-stress formulation of the equation of motion on a staggered grid. The nonreflecting boundary conditions are used to attenuate the wave field close to the numerical boundary. To satisfy the stress-free conditions at the free-surface boundary, a new formulation combining the zero-stress formalism with the vacuum one is applied. The effective media parameters are employed to satisfy the traction continuity condition across the media interface. With use of the moment-tensor components, the wide range of source mechanism parameters can be specified. The numerical experiments are carried out in order to test the applicability and accuracy of this scheme and to understand the fundamental features of the wave propagation under the generalized elastic media structure. Computational results show that the scheme is sufficiently accurate for modeling wave propagation in 3D elastic media and generates all the possible phases appropriately in under the given heterogeneous velocity structure. Also the characteristics of the ground motion in an sedimentary basin such as the amplification, trapping, and focusing of the elastic wave energy are well represented. These results demonstrate the use of this simulation method will be helpful for modeling the ground motion of seismological and engineering purpose like earthquake hazard assessment, seismic design, city planning, and etc..

• 대한전자공학회논문지SD
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• 제40권10호
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• pp.32-38
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• 2003

SIMOX 웨이퍼를 사용하여 제작된 GAA 구조 SOI MOSFET의 열전자에 의한 소자열화를 측정·분석하였다. nMOSFET의 열화는 스트레스 게이트 전압이 문턱전압과 같을 때 최대가 되었는데 이는 낮은 게이트 전압에서 PBT 작용의 활성화로 충격이온화가 많이 되었기 때문이다. 소자의 열화는 충격이혼화로 생성된 열전자와 홀에의한 계면상태 생성이 주된 원인임을 degradation rate와 dynamic transconductance 측정으로부터 확인하였다. 그리고 pMOSFET의 열화의 원인은 DAHC 현상에서 생성된 열전자 주입에 의한 전자 트랩핑이 주된 것임을 스트레스 게이트 전압변화에 따른 드레인 전류 변화로부터 확인 할 수 있었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.419-419
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• 2016

High efficiency silicon solar cell requires the textured front surface to reduce reflectance and to improve the light trapping. In case of mono-crystalline silicon solar cell, wet etching with alkaline solution is widespread. However, the alkali texturing methods are ineffective in case of multi-crystalline silicon wafer due to grain boundary of random crystallographic orientation. The acid texturing method is generally used in multi-crystalline silicon wafer to reduce the surface reflectance. However the acid textured solar cell gives low short-circuit current due to high reflectivity while it improves the open-circuit voltage. To reduce the reflectivity of multi-crystalline silicon wafer, double texturing method with combination of acid and reactive ion etching is an attractive technical solution. In this paper, we have studied to optimize RIE experimental condition with change of RF power (100W, 150W, 200W, 250W, 300W). During experiment, the gas ratio of SF6 and O2 was fixed as 30:10.

• 한국안광학회지
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• 제6권2호
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• pp.121-127
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• 2001

additive 감쇠에 의한 감쇠 최소 자승법에 가우스 소거법과 Jacobian 행렬을 직교 변환시킨 SVD(singular value decomposition)법을 적용하여 조건수가 양호한 triplet 사진 렌즈계에 적용하여 수렴 속도와 안정성을 비교하였다. SVD 직교화 방법을 적용한 감쇠 최소 자승 법이 최소 merit 함수에 보다 안정되고 빠르게 수렴하였다. SVD 방법을 적용한 최적화에서 적절한 merit 함수를 얻을 수 있지만 오차 함수의 비선형성으로 인해 merit 함수가 국부 최소 점에 수업하는 경우가 있어서 간단한 전역 최적화 방법인격자 법으로 최적화를 실시하여 SVD 방법에 의한 merit 함수보다 낮은 전역 최소 점에 수렴하게 하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 추계학술대회 논문집
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• pp.9-12
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• 1998

Film characteristics of thin reoxidized nitrided oxides were investigated by SIMS analysis and C-V method in order to use the gate dielectric for charge-trap type NVSMs instead of ONO stacked layers. Nitric oxide(NO) annealed film has the nitrogen content sharply peaked at the Si-SiO$_2$ interface, while it is broad for nitrous oxide($N_2$O) ambient. The nitrogen peak concentration increased with anneal temperature and time. The position of nitrogen content in the oxide layer was due to be precisely controlled. For the films annealed NO ambient at 80$0^{\circ}C$ for 30min. followed by reoxidized at 85$0^{\circ}C$, the maximum memory window of 3.5V was obtained and the program condition was +12V, 1msec for write and -l3V, 1msec for erase.