• 제목/요약/키워드: transpose

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THE GORENSTEIN TRANSPOSE OF COMODULES

  • Li, Yexuan;Yao, Hailou
    • Journal of the Korean Mathematical Society
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    • v.58 no.4
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    • pp.1019-1033
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    • 2021
  • Let 𝚪 be a Gorenstein coalgebra over a filed k. We introduce the Gorenstein transpose via a minimal Gorenstein injective copresentation of a quasi-finite 𝚪-comodule, and obtain a relation between a Gorenstein transpose of a quasi-finite comodule and a transpose of the same comodule. As an application, we obtain that the almost split sequences are constructed in terms of Gorenstein transpose.

Finite impulse response design based on two-level transpose Vedic multiplier for medical image noise reduction

  • Joghee Prasad;Arun Sekar Rajasekaran;J. Ajayan;Kambatty Bojan Gurumoorthy
    • ETRI Journal
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    • v.46 no.4
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    • pp.619-632
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    • 2024
  • Medical signal processing requires noise and interference-free inputs for precise segregation and classification operations. However, sensing and transmitting wireless media/devices generate noise that results in signal tampering in feature extractions. To address these issues, this article introduces a finite impulse response design based on a two-level transpose Vedic multiplier. The proposed architecture identifies the zero-noise impulse across the varying sensing intervals. In this process, the first level is the process of transpose array operations with equalization implemented to achieve zero noise at any sensed interval. This transpose occurs between successive array representations of the input with continuity. If the continuity is unavailable, then the noise interruption is considerable and results in signal tampering. The second level of the Vedic multiplier is to optimize the transpose speed for zero-noise segregation. This is performed independently for the zero- and nonzero-noise intervals. Finally, the finite impulse response is estimated as the sum of zero- and nonzero-noise inputs at any finite classification.

A Design of Velocity Type Digital Control Systems for Space Robots Using Transpose of GJM

  • Mahiro, Oya;Graefe, Volker
    • 제어로봇시스템학회:학술대회논문집
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    • 2001.10a
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    • pp.147.3-147
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    • 2001
  • We have proposed a digital control method, where the controlled variable is a joint angular velocity, of space robot manipulators using the transpose of Generalized Jacobian Matrix. The explicit relationship between the control law and the sampling period, however, is unknown because the controller gains include the sampling period implicitly. This paper presents a novel digital control method which explicitly describes the relation between the sampling period and the controller gains. Computer simulation of a 3-DOF planar space robot manipulator is peformed. Simulation result demonstrates the effctiveness of the proposed method.

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COMPUTATION OF SOMBOR INDICES OF OTIS(BISWAPPED) NETWORKS

  • Basavanagoud, B.;Veerapur, Goutam
    • Journal of the Chungcheong Mathematical Society
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    • v.35 no.3
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    • pp.205-225
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    • 2022
  • In this paper, we derive analytical closed results for the first (a, b)-KA index, the Sombor index, the modified Sombor index, the first reduced (a, b)-KA index, the reduced Sombor index, the reduced modified Sombor index, the second reduced (a, b)-KA index and the mean Sombor index mSOα for the OTIS biswapped networks by considering basis graphs as path, wheel graph, complete bipartite graph and r-regular graphs. Network theory plays a significant role in electronic and electrical engineering, such as signal processing, networking, communication theory, and so on. A topological index (TI) is a real number associated with graph networks that correlates chemical networks with a variety of physical and chemical properties as well as chemical reactivity. The Optical Transpose Interconnection System (OTIS) network has recently received increased interest due to its potential uses in parallel and distributed systems.

2-D DCT/IDCT Processor Design Reducing Adders in DA Architecture (DA구조 이용 가산기 수를 감소한 2-D DCT/IDCT 프로세서 설계)

  • Jeong Dong-Yun;Seo Hae-Jun;Bae Hyeon-Deok;Cho Tae-Won
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.3 s.345
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    • pp.48-58
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    • 2006
  • This paper presents 8x8 two dimensional DCT/IDCT processor of adder-based distributed arithmetic architecture without applying ROM units in conventional memories. To reduce hardware cost in the coefficient matrix of DCT and IDCT, an odd part of the coefficient matrix was shared. The proposed architecture uses only 29 adders to compute coefficient operation in the 2-D DCT/IDCT processor, while 1-D DCT processor consists of 18 adders to compute coefficient operation. This architecture reduced 48.6% more than the number of adders in 8x8 1-D DCT NEDA architecture. Also, this paper proposed a form of new transpose network which is different from the conventional transpose memory block. The proposed transpose network block uses 64 registers with reduction of 18% more than the number of transistors in conventional memory architecture. Also, to improve throughput, eight input data receive eight pixels in every clock cycle and accordingly eight pixels are produced at the outputs.

Optimization of Pipelined Discrete Wavelet Packet Transform Based on an Efficient Transpose Form and an Advanced Functional Sharing Technique

  • Nguyen, Hung-Ngoc;Kim, Cheol-Hong;Kim, Jong-Myon
    • Journal of Information Processing Systems
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    • v.15 no.2
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    • pp.374-385
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    • 2019
  • This paper presents an optimal implementation of a Daubechies-based pipelined discrete wavelet packet transform (DWPT) processor using finite impulse response (FIR) filter banks. The feed-forward pipelined (FFP) architecture is exploited for implementation of the DWPT on the field-programmable gate array (FPGA). The proposed DWPT is based on an efficient transpose form structure, thereby reducing its computational complexity by half of the system. Moreover, the efficiency of the design is further improved by using a canonical-signed digit-based binary expression (CSDBE) and advanced functional sharing (AFS) methods. In this work, the AFS technique is proposed to optimize the convolution of FIR filter banks for DWPT decomposition, which reduces the hardware resource utilization by not requiring any embedded digital signal processing (DSP) blocks. The proposed AFS and CSDBE-based DWPT system is embedded on the Virtex-7 FPGA board for testing. The proposed design is implemented as an intellectual property (IP) logic core that can easily be integrated into DSP systems for sub-band analysis. The achieved results conclude that the proposed method is very efficient in improving hardware resource utilization while maintaining accuracy of the result of DWPT.

Force Controller of the Redundant Manipulator using Seural Network (Redundant 매니퓰레이터의 force 제어를 위한 신경 회로망 제어기)

  • 이기응;조현찬;전홍태;이홍기
    • 제어로봇시스템학회:학술대회논문집
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    • 1990.10a
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    • pp.13-17
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    • 1990
  • In this paper we propose the force controller using a neural network for a redundant manipulator. Jacobian transpose matrix of a redundant manipulator constructed by a neural network is trained by using a feedback torque as an error signal. If the neural network is sufficiently trained well, the kinematic inaccuracy of a manipulator is automatically compensated. The effectiveness of the proposed controller is demonstrated by computer simulation using a three-link planar robot.

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Hybrid position/force controller design of the robot manipulator using neural network (신경 회로망을 이용한 로보트 매니퓰레이터의 Hybrid 위치/힘 제어기의 설계)

  • 조현찬;전홍태;이홍기
    • 제어로봇시스템학회:학술대회논문집
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    • 1990.10a
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    • pp.24-29
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    • 1990
  • In this paper ,ie propose a hybrid position/force controller of a robot manipulator using double-layer neural network. Each layer is constructed from inverse dynamics and Jacobian transpose matrix, respectively. The weighting value of each neuron is trained by using a feedback force as an error signal. If the neural networks are sufficiently trained it does not require the feedback-loop with error signals. The effectiveness of the proposed hybrid position/force controller is demonstrated by computer simulation using a PUMA 560 manipulator.

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AN ALGORITHM FOR CHECKING EXTREMALITY OF ENTANGLED STATES WITH POSITIVE PARTIAL TRANSPOSES

  • Ha, Kil-Chan
    • Journal of the Chungcheong Mathematical Society
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    • v.23 no.4
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    • pp.609-616
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    • 2010
  • We characterize extreme rays of the cone $\mathbb{T}$ of all positive semi-definite block matrices whose partial transposes are also positive semi-definite. We also construct an algorithm checking whether a given PPTES generates an extreme ray in the cone $\mathbb{T}$ or not. Using this algorithm, we give an example of $4{\otimes}4$ PPT entangle state of the type (5, 5), which generates extreme ray of the cone $\mathbb{T}$.