• KEPCO Journal on Electric Power and Energy
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• 제2권2호
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• pp.223-225
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• 2016

The newly proposed analysis method using a direct-current current-voltage (DCIV) simulation is introduced for investigating leakage current composing MOS transistor. From comparing the density and location of traps using DCIV method and investigating the leakage current of gate channel transistor, we proposed the graphical analysis method to correlate the DCIV current and leakage mechanism by the traps. And, our graphical method intuitively explains that leakage current in MOS transistor is well correlated with the DCIV current of the MOS transistor arrays due to two kinds of traps created by Fowler-Nordheim (F-N) stress and Hot carrier stress, respectively.

• 전력전자학회논문지
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• 제6권5호
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• pp.453-459
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• 2001

본 논문에서는 Two-transistor 포워드 컨버터에서 사용 가능한 기존의 소프트 스위칭 기법과 새로운 소프트 스위칭 기법의 손실 분석을 수행한다. 두 트랜지스터에서 발생하는 스너버 전류에 의한 트랜지스터 손실과 내부 커패시터에 의한 턴-온 손실을 유도하고, 각각의 트랜지스터에서 발생하는 전체 손실을 계산한다. 손실 계산을 통해 기존의 소프트 스위칭 기법에서는 두 트랜지스터에서 발생하는 손실이 상이함을 보이고, 새로운 소프트 스위칭 기법에서는 손실이 적으면서도 두 트랜지스터에서의 손실이 고르게 발생함을 알 수 있다. 그리하여 제안된 소프트 스위칭 스너버를 사용하여 고른 열분포와 향상된 신뢰도를 얻을 수 있음을 보인다.

• 전기학회논문지
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• 제57권4호
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• pp.653-659
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• 2008

This paper describes the design of high power transistor packages using high power chip transistor dies, chip capacitors and a new wire bonding technique. Input impedance variation and output power performances according to wire inductance and resistance for internal matching are also discussed. A multi crossing type(MCT) wire bonding technique is proposed to replace the conventional stepping stone type(SST) wire bonding technique, and eventually to improve the output power performances of high power transistor packages. Using the proposed MCT wire bonding technique, it is possible to design high power transistor packages with highly improved output power compared to SST even the package size is kept to be the same.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.59-62
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• 2000

A VLSI implementation of a self-learning neural network integrated circuits using a linearity synapse transistor is investigated. The thickness dependence of oxide current density, stress current, transient current and channel current has been measured in oxides with thicknesses between 41 and 112 $\AA$, which have the channel width$\times$length 10$\times$1${\mu}{\textrm}{m}$ respectively. The transient current will affect data retention in synapse transistors and the stress current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor has represented the neural states and the manipulation which gave unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the drain source current.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.302-317
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• 2017

This paper proposes a new full adder design based on pass-transistor logic that offers ultra-low power dissipation and superior variability together with low transistor count. The pass-transistor logic allows device count reduction through direct logic realization, and thus leads to reduction in the node capacitances as well as short-circuit currents due to the absence of supply rails. Optimum transistor sizing alleviates the adverse effects of process variations on performance metrics. The design is subjected to a comparative analysis against existing designs based on Monte Carlo simulations in a SPICE environment, using the 22-nm CMOS Predictive Technology Model (PTM). The proposed ULP adder offers 38% improvement in power in comparison to the best performing conventional designs. The trade-off in delay to achieve this power saving is estimated through the power-delay product (PDP), which is found to be competitive to conventional values. It also offers upto 79% improvement in variability in comparison to conventional designs, and provides suitable scalability in supply voltage to meet future demands of energy-efficiency in portable applications.

• 센서학회지
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• 제21권6호
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• pp.413-419
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• 2012

A dynamic range extension technique is proposed based on a 3-transistor active pixel sensor (APS) with gate/body-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector using a feedback structure. The new APS consists of a pseudo 3-transistor APS and an additional gate/body-tied PMOSFET-type photodetector, and to extend the dynamic range, an NMOSFET switch is proposed. An additional detector and an NMOSFET switch are integrated into the APS to provide negative feedback. The proposed APS and pseudo 3-transistor APS were designed and fabricated using a $0.35-{\mu}m$ 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) process. Afterwards, their optical responses were measured and characterized. Although the proposed pixel size increased in comparison with the pseudo 3-transistor APS, the proposed pixel had a significantly extended dynamic range of 98 dB compared to a pseudo 3-transistor APS, which had a dynamic range of 28 dB. We present a proposed pixel that can be switched between two operating modes depending on the transfer gate voltage. The proposed pixel can be switched between two operating modes depending on the transfer gate voltage: normal mode and WDR mode. We also present an imaging system using the proposed APS.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권2호
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• pp.69-75
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• 2003

Cell transistor and data retention time characteristics were studied in 90 nm design rule 512M-bit DRAM, for the first time. And, the characteristics of cell transistor are investigated for different STI gap-fill materials. HDP oxide with high compressive stress increases the threshold voltage of cell transistor, whereas the P-SOG oxide with small stress decreases the threshold voltage of cell transistor. Stress between silicon and gap-fill oxide material is found to be the major cause of the shift of the cell transistor threshold voltage. If high stress material is used for STI gap fill, channel-doping concentration can be reduced, so that cell junction leakage current is decreased and data retention time is increased.

• 전자공학회논문지
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• 제52권3호
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• pp.59-66
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• 2015

본 논문에서는 4bit SAR-ADC(Successive Approximation ADC) 기반의 LDO(Low Drop-Out Regulator)와 파워 트랜지스터의 사이즈 선택을 통하여 DC-DC 벅 컨버터의 효율을 개선하는 방법을 제안한다. 제안하는 회로는 부하 전류에 따라서 파워 트랜지스터 사이즈를 선택하여 DC-DC 벅 컨버터의 효율을 개선한다. 이를 위해, 우리는 스위칭 손실과 전도 손실이 교차하는 지점을 파워 트랜지스터의 적절한 사이즈로 선택하였다. 또한, standby mode 또는 sleep mode로 동작 시에는 효율을 개선하기 위해 LDO로 동작하도록 하였다. 제안하는 회로는 4bit로 파워 트랜지스터 사이즈(X1, X2, X4, X8)를 선택하였고, 저부하에서 단일 사이즈를 이용한 기존의 방식보다 최대 25%의 효율 개선을 얻을 수 있었다. 입력 전압은 5V, 출력 전압은 3.3V, 최대 부하 전류는 500mA이다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1997년도 한국재료학회 추계학술발표회
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• pp.159-159
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• 1997

• 전기전자학회논문지
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• 제12권4호
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• pp.211-216
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• 2008

이 논문은 MOS 전류모드 논리 (MOS current-mode logic circuit, MCML) 회로를 이용하여 저 전력 특성을 갖는 8${\times}$8 비트 병렬 곱셈기를 설계하였다. 설계한 곱셈기는 회로가 동작 하지 않을 때의 정적 전류의 소모를 최소화하기 위하여 슬립 트랜지스터 (sleep-transistor)를 이용하여 저 전력 MOS 전류모드 논리회로를 구현하였다. 설계한 곱셈기는 기존 MOS 전류모드 논리회로에 비해 대기전력소모가 1/50으로 감소하였다. 또한, 이 회로는 기존 MOS 전류모드 논리회로에 비해 전력소모에서 10.5% 감소하였으며, 전력소모와 지연시간의 곱에서 11.6%의 성능 향상이 있었다. 이 회로는 삼성 0.35${\mu}m$ 표준 CMOS 공정을 이용하여 설계하였으며, HSPICE를 통하여 검증하였다.