• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.4
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• pp.502-509
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• 2013

It presents an efficient switching pattern, which expects a reduction of switching losses in a cascaded H-bridge PWM multilevel inverter. By the proposed switching scheme, the lower H-bridge module operates at low frequency of 60[Hz] because it assigns to transfer most load power. The upper H-bridge module operates at high frequency of PWM switching to improve THD of output voltage. The proposed switching pattern applies to cascaded H-bridge multilevel inverter with PD, APOD, bipolar, and unipolar switching methods. By computer-aided simulations, we verify the validity of the proposed switching scheme. Finally, we prove that the proposed PD and APOD switching patterns are better than those of the conventional one in efficiency.

• Journal of Power Electronics
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• v.15 no.3
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• pp.670-684
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• 2015

The hybrid cascaded multilevel inverter (HCMLI) is a popular converter topology that is being increasingly used in high power medium voltage drives. The intricacy of the control technique for a HCMLI increases with the number of levels and due to fluctuating dc voltages. This paper presents a novel offline quadrant search based space vector modulation technique to synthesize a sinusoidal output from a dispersed pattern of voltage vectors due to different voltages in the auxiliary unit. Such an investigation has never been reported in the literature and it is being attempted for the first time. The method suggested distributes the voltage vectors for a reduced total harmonic distortion at minimal computation. In addition, the proposed algorithm determines the maximum modulation index in the linear modulation range in order to synthesize a sinusoidal output for both normal and abnormal vector patterns. It is better suited for a wide range of practical applications. It is particularly well suited for renewable source fed inverters which utilize large capacitor banks to maintain the dc link, which are prone to such slow fluctuations. The proposed quadrant search space vector modulation technique is simulated using MATLAB/SIMULINK and implemented using a Nexys-2 Spartan-3E FPGA for a developed prototype.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.4
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• pp.322-332
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• 2013

Conventional single-phase series quasi Z-source voltage compensator can not compensate for voltage sag less than 50% that frequently occurs in the industrial field. In this study, single-phase series quasi Z-source voltage sag-swell compensator which can compensate the voltage variation of entire range is proposed. The proposed system is composed of two quasi Z-source AC-AC converters connected in series with output terminal stage. Voltage sag less than 50% could be compensated by the intersection switching control of the upper converter duty ratio and of the upper converter duty ratio. Also the compensation voltage and its flowchart for each compensation mode are presented for entire sag-swell region. To confirm the validity of the proposed system, a DSP(DSP28335) controlled experimental system was manufactured. As a result, the proposed system could compensate for the voltage sag/swell of 20% and 60%. Finally, voltage compensation factor and THD(Total Harmonic Distortion) according to voltage variation and load change were measured, and voltage quality shows a good results.

• Journal of Power Electronics
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• v.12 no.1
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• pp.104-112
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• 2012

In this paper a new method for the design of a simple PI controller is presented and it has been applied in the control of a Boost based PFC rectifier. The Strength Pareto evolutionary algorithm, which is based on the Pareto Optimality concept, used in Game theory literature is implemented as a multi-objective optimization approach to gain a good transient response and a high quality input current. In the proposed method, the input current harmonics and the dynamic response have been assumed as objective functions, while the PI controller's gains of the PFC rectifier (Kpi, Tpi) are design variables. The proposed algorithm generates a set of optimal gains called a Pareto Set corresponding to a Pareto Front, which is a set of optimal results for the objective functions. All of the Pareto Front points are optimum, but according to the design priority objective function, each one can be selected. Simulation and experimental results are presented to prove the superiority of the proposed design methodology over other methods.

• ETRI Journal
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• v.31 no.5
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• pp.576-584
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• 2009

A novel tunable transconductor is presented. Input transistors operate in the triode region to achieve programmable voltage-to-current conversion. These transistors are kept in the triode region by a novel negative feedback loop which features simplicity, low voltage requirements, and high output resistance. A linearity analysis is carried out which demonstrates how the proposed transconductance tuning scheme leads to high linearity in a wide transconductance range. Measurement results for a 0.5 ${\mu}m$ CMOS implementation of the transconductor show a transconductance tuning range of more than a decade (15 ${\mu}A/V$ to 165 ${\mu}A/V$) and a total harmonic distortion of -67 dB at 1 MHz for an input of 1 Vpp and a supply voltage of 1.8 V.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.955-959
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• 2003

A technique for realizing linear phase IIR filters has been proposed by Powell-Chau which gives a real-time implementation of H(z-1).H(z), where H(z) is a causal nonlinear phase IIR filter. Powell-Chau system is linear but not timeinvariant system. Therefore, that system has group delay response that exhibits a minor sinusoidal variation superimposed on a constant value. In the signal processing, this oscillation seriously degrade the signal quality. Unfortunately, that system has a large sample delay of 4L and also more computational complexity. Proposed system is present a reduced computational complexity technique by moved the numerator polynomial of H(1/z) out to cascade with causal filter H(z) and remain only all-pole of H(1/z), then applied truncated infinite impulse response to finite with truncated IIR filtel $H_L$(z) and L sample delay to subtract the output sequence from the top and bottom filter. Proposed system is linear time invariance and group delay response and total harmonic distortion are also improved.

• Journal of international Conference on Electrical Machines and Systems
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• v.1 no.4
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• pp.457-463
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• 2012

Cascaded H-bridge multilevel inverters shows a useful circuit configuration to increase the number of output voltage levels to obtain high quality output voltage. By applying the concept of the power of three to dc voltage sources, it can increase the number of output voltage levels effectively. To realize this concept, two approaches may be considered. One is to use independent dc voltage sources pre-scaled in the power of three, and the other is to use instantaneous dc voltage sources generated from a cascaded transformer, which has the secondary turn-ratios scaled in the power of three in sequence. A common feature in both approaches is to use the concept of the power of three for dc voltage sources, and a point of difference is whether it adopts a low frequency transformer or not, and where the transformer is located. According to the difference, application areas are limited and show different characteristics on THD of output voltages. We compare and analyze both approaches for their circuit configurations, voltage level generating method, THD characteristics of output voltage, efficiency, application areas, limitations, and other characteristics by experiments using 500 [W] prototypes when they generate a 27-level output voltage.

• Journal of the Korean Society of Marine Environment & Safety
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• v.24 no.3
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• pp.373-380
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• 2018

The small coastal vessel registered in Korea, small coastal vessels with a gross tonnage of 10 tons or less account for 94.6 % and among them, aged vessels over 16 years age indicate 40.6 %. In order to reduce GHG emissions from small coast vessels, discussions are underway to replace aging ships' propulsion units with eco - friendly propulsion facilities, and the electric propulsion ship is emerging as one of the measures. The electric propulsion system using the DFE rectifier, which was applied in the conventional large commercial vessel, was effective in reducing the harmonics and improving the DC output voltage of the DC link stage, but it occupied a large volume and caused an increase in the overall system price. Therefore, in this paper, we propose an electric propulsion system using AFE rectifier with a small volume of system that can be applied to a small coastal vessel. In order to analyze the effectiveness of the overall system, the load profile was applied to obtain accurate and rapid speed tracking performance of the propulsion motor affected by the speed load. In addition, the power factor and total harmonic distortion factor of the voltage and current on the improved power output side are derived through simulation.

• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1674-1683
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• 2016

In this paper, a Finite Control Set Model Predictive Control (FCS-MPC) for a five level cascaded multilevel inverter (CMLI) with reduced switch topology is proposed. Five switches are used here instead of conventionally used eight switches. The main contribution of this paper is to make the MPC controller work for the reduced switch topology using only 19 voltage vectors in place of conventional 61 voltage vectors for a five level CMLI. This simplifies the execution of the MPC algorithm, paving a way for the significant reduction in the computational time. The controller makes use of the excellent ability of MPC to multitask, by adding one more objective which is to reduce the average switching frequency in addition to controlling the load current. This is especially important, since switching losses and therefore switching frequency is significant for high-power applications. The trade-off of this MPC is that the current is not as smooth as the 61 vector scheme, but well within the limits of IEEE standards. The results shown prove that this MPC works well in steady state and dynamic conditions too.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.4
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• pp.283-289
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• 2016

Islanding protection of a grid-connected photovoltaic (PV) inverter is a key function for standards compliance. Unintentional islanding results in safety hazards, reliability, and many other issues. Therefore, many anti-islanding schemes have been examined. However, existing anti-islanding schemes have poor power quality and non-detection zone issues. Moreover, most schemes have problems that deteriorate the performance of islanding detection under parallel operation. Therefore, this paper proposes a novel anti-islanding scheme that has negligible power quality degradation and has no non-detection zone and islanding detection under a parallel operation. Both simulation and experimental results validate the proposed scheme.