• Title/Summary/Keyword: top-gate structure

Search Result 69, Processing Time 0.027 seconds

Graphene for MOS Devices

  • Jo, Byeong-Jin
    • Proceedings of the Materials Research Society of Korea Conference
    • /
    • 2012.05a
    • /
    • pp.67.1-67.1
    • /
    • 2012
  • Graphene has attracted much attention for future nanoelectronics due to its superior electrical properties. Owing to its extremely high carrier mobility and controllable carrier density, graphene is a promising material for practical applications, particularly as a channel layer of high-speed FET. Furthermore, the planar form of graphene is compatible with the conventional top-down CMOS fabrication processes and large-scale synthesis by chemical vapor deposition (CVD) process is also feasible. Despite these promising characteristics of graphene, much work must still be done in order to successfully develop graphene FET. One of the key issues is the process technique for gate dielectric formation because the channel mobility of graphene FET is drastically affected by the gate dielectric interface quality. Formation of high quality gate dielectric on graphene is still a challenging. Dirac voltage, the charge neutral point of the device, also strongly depends on gate dielectrics. Another performance killer in graphene FET is source/drain contact resistance, as the contact resistant between metal and graphene S/D is usually one order of magnitude higher than that between metal and silicon S/D. In this presentation, the key issues on graphene-based FET, including organic-inorganic hybrid gate dielectric formation, controlling of Dirac voltage, reduction of source/drain contact resistance, device structure optimization, graphene gate electrode for improvement of gate dielectric reliability, and CVD graphene transfer process issues are addressed.

  • PDF

Pentacene Thin Film Transistors with Various Polymer Gate Insulators

  • Kim, Jae-Kyoung;Kim, Jung-Min;Yoon, Tae-Sik;Lee, Hyun-Ho;Jeon, D.;Kim, Yong-Sang
    • Journal of Electrical Engineering and Technology
    • /
    • v.4 no.1
    • /
    • pp.118-122
    • /
    • 2009
  • Organic thin film transistors with a pentacene active layer and various polymer gate insulators were fabricated and their performances were investigated. Characteristics of pentacene thin film transistors on different polymer substrates were investigated using an atomic force microscope (AFM) and x-ray diffraction (XRD). The pentacene thin films were deposited by thermal evaporation on the gate insulators of various polymers. Hexamethyldisilazane (HMDS), polyvinyl acetate (PVA) and polymethyl methacrylate (PMMA) were fabricated as the gate insulator where a pentacene layer was deposited at 40, 55, 70, 85, 100 oC. Pentacene thin films on PMMA showed the largest grain size and least trap concentration. In addition, pentacene TFTs of top-contact geometry are compared with PMMA and $SiO_2$ as gate insulators, respectively. We also fabricated pentacene TFT with Poly (3, 4-ethylenedioxythiophene)-Polysturene Sulfonate (PEDOT:PSS) electrode by inkjet printing method. The physical and electrical characteristics of each gate insulator were tested and analyzed by AFM and I-V measurement. It was found that the performance of TFT was mainly determined by morphology of pentacene rather than the physical or chemical structure of the polymer gate insulator

Dependence of Conduction Path for Device Parameter of DGMOSFET Using Series (급수를 이용한 DGMOSFET에서 소자 파라미터에 대한 전도중심 의존성)

  • Han, Jihyung;Jung, Hakkee;Jeong, Dongsoo;Lee, Jongin;Kwon, Ohshin
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2012.10a
    • /
    • pp.835-837
    • /
    • 2012
  • In this paper, we have been analyzed conduction path by device parameter of double gate(DG) structure that have top gate and bottom gate. The Possion equation is used to analytical. The change of conduction path have been investigated for various channel lengths, channel thickness and gate oxide thickness using this model, given that these parameters are very important in design of DGMOSFET. The optimum channel doping concentration is determined as the deviation of conduction path is considered according to channel doping concentration.

  • PDF

Study on the Organic Gate Insulators Using VDP Method (VDP(Vapor Deposition Polymerization) 방법을 이용한 유기 게이트 절연막의 대한 연구)

  • Pyo, Sang-Woo;Shim, Jae-Hoon;Kim, Jung-Soo;Kim, Young-Kwan
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2003.07a
    • /
    • pp.185-190
    • /
    • 2003
  • In this paper, it was demonstrated that the organic thin film transistors were fabricated by the organic gate insulators with vapor deposition polymerization (VDP) processing. In order to form polyimide as a gate insulator, vapor deposition polymerization process was also introduced instead of spin-coating process, where polyimide film was co-deposited by high-vacuum thermal evaporation from 4,4'-oxydiphthalic anhydride (ODPA) and 4,4'-oxydianiline (ODA) and 2,2-bis(3,4-dicarboxyphenyl)hexafluoropropane dianhydride (6FDA) and ODA, and cured at $150^{\circ}C$ for 1hr. Electrical output characteristics in our organic thin film transistors using the staggered-inverted top-contact structure obtained to the saturated slop in the saturation region and the subthreshold non-linearity in the triode region. Field effect mobility, threshold voltage, and on-off current ratio in $0.45\;{\mu}m$ thick gate dielectric layer were about $0.17\;cm^2/Vs$, -7 V, and $10^6\;A/A$, respectively. Details on the explanation of compared to organic thin-film transistors (OTFTS) electrical characteristics of ODPA-ODA and 6FDA-ODA as gate insulators by fabricated thermal co-deposition method.

  • PDF

ZnO TFT with Organic Dielectric (유기절연체를 사용한 ZnO 박막트랜지스터)

  • Choi, Woon-Seop
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2008.11a
    • /
    • pp.56-56
    • /
    • 2008
  • ZnO Oxide TFT with organic dielectric was prepared. ZnO thin film as active channel was prepared by plasma enhanced atomic deposition technique. Organic dielectric was spin coated on the gate metal. The structure of prepared TFT is bottom gate type and top contact structure. The characterization of oxide TFT was performed. We obtained the mobility of $0.7cm^2$/Vs, the threshold voltage of -14V, and the on-off ratio of $10^4$. We also obtained good output characterization with solid saturation.

  • PDF

SIMULATION OF THIN-FILM FIELD EMITTER TRIODE

  • Park, Kyung-Ho;Lee, Soon-Il;Koh, Ken-Ha
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 2002.08a
    • /
    • pp.651-654
    • /
    • 2002
  • We carried out 2-dimensional numerical calculations of electrostatic potential for triode field emitters with planar cathodes using the finite element method. As it turned out, the conventional triode structure with a planar cathode suffered from large gate current and wide spreading of emitted electrons. To circumvent these shortcomings, we proposed a new triode structure. By simply inserting a conducting layer of proper thickness on top of the cathode layer, we were able to modify the electric field distribution on the cathode surface so that low gate current and electron-focusing effect were achieved, simultaneously.

  • PDF

Study on the Characteristics of Organic TFT Using Organic Insulating Layer Efficiency (유기 절연층에 따른 유기 TFT 특성 연구)

  • Pyo, Sang-Woo;Lee, Min-Woo;Sohn, Byung-Chung;Kim, Young-Kwan
    • Journal of the Korean Applied Science and Technology
    • /
    • v.19 no.4
    • /
    • pp.335-338
    • /
    • 2002
  • A new process for polymeric gate insulator in field-effect transistors was proposed. Fourier transform infrared absorption spectra were measured in order to identify ODPA-ODA polyimide. Its breakdown field and electrical conductivity were measured. All-organic thin-film transistors with a stacked-inverted top-contact structure were fabricated to demonstrate that thermally evaporated polyimide films could be used as a gate insulator. As a result, the transistor performances with evaporated polyimide was similar with spin-coated polyimide. It seems that the mass-productive in-situ solution-free processes for all-organic thin-film transistors are possible by using the proposed method without vacuum breaking.

Electrical Effects in Organic Thin-Film Transistors Using Polymerized Gate Insulators by Vapor Deposition Polymerization (VDP)

  • Lee, Dong-Hyun;Pyo, Sang-Woo;Koo, Ja-Ryong;Kim, Jun-Ho;Shim, Jae-Hoon;Kim, Young-Kwan
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 2004.08a
    • /
    • pp.661-664
    • /
    • 2004
  • In this paper, it was demonstrated that the organic thin film transistors with the organic gate insulators were fabricated by vapor deposition polymerization (VDP) processing. The configuration of OTFTs was a staggered-inverted top-contact structure and gate dielectric layer was deposited with 0.45 ${\mu}m$ thickness. In order to form polyimide as a gate insulator, VDP process was also introduced instead of spin-coating process. Polyimide film was respectively co-deposited with different materials. One was from a 4,4'-oxydiphthalic anhydride (ODPA) and 4, 4'-oxydianiline (ODA) and the other was from 2,2-bis(3,4-dicarboxyphenyl) hexafluoropropane dianhydride (6FDA) and ODA. And it was also cured at 150 $^{\circ}C$ for 1 hour followed by 200 $^{\circ}C$ for 1 hour. Electrical characteristics of the organic thin-film transistors were detailed comparisons between the ODPA-ODA and the 6FDA-ODA which were used as gate insulator.

  • PDF

AC Electrical Coupling of Monolithic 3D Inverter Consisting of Junctionless FET (Junctionless FET로 구성된 적층형 3차원 인버터의 AC 특성에 대한 연구)

  • Kim, Kyung-won;Ahn, Tae-Jun;Yu, Yun Seop
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2017.05a
    • /
    • pp.529-530
    • /
    • 2017
  • Electrical coupling of monolithic 3D inverter(M3D-INV) consisting of Junctionless FET(JLFET) was investigated. Depending on the thickness of Inter Layer Dielectirc (ILD) between top and bottom JLFETs, $N_{gate}-N_{gate}$ capacitance and transconductance $g_m$ are changed by the gate voltage of bottom JLFET. Therefore, when using a stacked structure with the ILD below tens nm, AC electrical coupling between two transistors in M3D-INV should be considered.

  • PDF

Metal Oxide Thin Film Transistor with Porous Silver Nanowire Top Gate Electrode for Label-Free Bio-Relevant Molecules Detection

  • Yu, Tae-Hui;Kim, Jeong-Hyeok;Sang, Byeong-In;Choe, Won-Guk;Hwang, Do-Gyeong
    • Proceedings of the Korean Vacuum Society Conference
    • /
    • 2016.02a
    • /
    • pp.268-268
    • /
    • 2016
  • Chemical sensors have attracted much attention due to their various applications such as agriculture product, cosmetic and pharmaceutical components and clinical control. A conventional chemical and biological sensor is consists of fluorescent dye, optical light sources, and photodetector to quantify the extent of concentration. Such complicated system leads to rising cost and slow response time. Until now, the most contemporary thin film transistors (TFTs) are used in the field of flat panel display technology for switching device. Some papers have reported that an interesting alternative to flat panel display technology is chemical sensor technology. Recent advances in chemical detection study for using TFTs, benefits from overwhelming progress made in organic thin film transistors (OTFTs) electronic, have been studied alternative to current optical detection system. However numerous problems still remain especially the long-term stability and lack of reliability. On the other hand, the utilization of metal oxide transistor technology in chemical sensors is substantially promising owing to many advantages such as outstanding electrical performance, flexible device, and transparency. The top-gate structure transistor indicated long-term atmosphere stability and reliability because insulator layer is deposited on the top of semiconductor layer, as an effective mechanical and chemical protection. We report on the fabrication of InGaZnO TFTs with silver nanowire as the top gate electrode for the aim of chemical materials detection by monitoring change of electrical properties. We demonstrated that the improved sensitivity characteristics are related to the employment of a unique combination of nano materials. The silver nanowire top-gate InGaZnO TFTs used in this study features the following advantages: i) high sensitivity, ii) long-term stability in atmosphere and buffer solution iii) no necessary additional electrode and iv) simple fabrication process by spray.

  • PDF