• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.5
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• pp.361-369
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• 1991

The optics and the signal processor of dual beam laser Doppler velocimeter(LDV) was fabricated. By using the dual beam and the forward scattering, the optics part of LDV was fabricated. And the signal processor of LDV was designed by the frequency counter type using new 11:6 period timing device in order to remove error signals, and was made of the reference clock of a 500 MHz ECL oscillator. Doppler frequencies from 10KHz to 70MHz can be measured using the signal processor. In the accuracy of the period counting part, from 1.81x10**-4% to 1.27% is estimated, and in the accuracy of the validation logic part, from 0.78% to 14.78% is estimated.

• Journal of the Korean Society for Aviation and Aeronautics
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• v.23 no.3
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• pp.35-41
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• 2015

Multilateration(MLAT) is commonly used in civil and military surveillance applications to accurately locate an aircraft, vehicle or stationary emitter. MLAT calculates the TDOA of signals by transmitted aircraft and determines the aircraft's location. With more than four receivers it is possible to estimate the 3D position of the aircraft by calculating the intersection of the resulting hyperbolas and the system integrity. In this study, our objectives are to apply MLAT technique to Jeju terminal control area and to propose a MLAT receiver network to properly estimate the positions of aircraft approaching this area. Based on computer simulations, we determine locations of ground receivers in Jeju terminal control area, calculate estimated position errors of the aircraft with respect to the selected receiver networks, and find the best receiver network with the least position error.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.906-911
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• 2008

This paper designed Simulik Model to cancel the carrier frequency offset in OFDM using CORDIC Algorithm and evaluated its performance. And Simulink Model compared with Xilinx System Generator Model for FPGA implementation. As a result of simulation, we confirmed that both model is error free by CORDIC when offset frequency is lower than $10^5MHz$. Also, we verified the performance through Hardware Co-simulation with Xilinx Spartan3 xc3s1000 fg676-4 Target Device, and timing analysis and resource estimation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.485-488
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• 2009

The class of BCH codes is a large class of error correction codes. HDL implementation of BCH code generator to change code rate. and used System Generator, and implemented hardware to FPGA. Loaded bit stream to a FPGA board in order to verify this design to Hardware co-simulation from these results. Also, compared as investigated the maximum action frequency through timing analysis and resource of logic in order to evaluate performance of BCH code generator.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.136-142
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• 2013

CRC features have been added to increase the reliability of the data in memory products for high-speed operation, such as DDR4. High-speed memory products in a shortage of internal timing margin increases for the CRC calculation. Because the existing CRC requires many additional circuit area and delay time. In this paper, we show that the matrix-type CRC and a new XOR/XNOR gate could be improved the circuit area and delay time. Proposed matrix-type CRC can detect all odd-bit errors and can detect even number of bit errors, except for multiples of four bits. In addition, a single error in the error correction can reduce the burden of re-transmission of data between memory products and systems due to CRC errors. In addition, the additional circuit area, compared to existing methods can be improved by 57%. The proposed XOR gate which is consists of six transistors, it can reduce the area overhead of 35% compared to the existing CRC, 50% of the gate delay can be reduced.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.3
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• pp.577-582
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• 2016

The synchronous TDC(Time-to-Digital Converter) of counter-type using current-conveyor is designed by $0.18{\mu}m$ CMOS process and the supply voltage is 3 volts. In order to compensate the disadvantage of a asynchronous TDC the clock is generated when the start signal is applied and the clock is synchronized with the start signal. In the asynchronous TDC the error range of digital output is from $-T_{CK}$ to $T_{CK}$. But the error range of digital output is from 0 to $T_{CK}$ in the synchronous TDC. The error range of output is reduced by the synchronization between the start signal and the clock when the timing-interval signal is converted to digital value. Also the structure of the synchronous TDC is simple because there is no the high frequency external clock. The operation of designed TDC is confirmed by the HSPICE simulation.

• Journal of IKEEE
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• v.19 no.3
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• pp.288-294
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• 2015

CRC function has been built into the high-speed semiconductor memory device in order to increase the reliability of data for high-speed operation. Also, DBI function is adopted to improve of data transmission speed. Conventional CRC(ATM-8 HEC code) method has a significant amounts of area-overhead(~XOR 700 gates), and processing time(6 stage XOR) is large. Therefore it leads to a considerable burden on the timing margin at the time of reading and writing of the low power memory devices for CRC calculations. In this paper, we propose a CRC method for low cost and high speed memory, which was improved 92% for area-overhead. For low-cost implementation of the CRC scheme by the DBI function it was supplemented by data bit error detection rate. And analyzing the error detection rate were compared with conventional CRC method.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.4
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• pp.129-135
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• 2011

The alternate adaptation algorithm (AAA) is proposed to improve the convergence characteristics and steady-state performance of the constant modulus algorithm (CMA). The alternate adaptation algorithm is a new equalization method which adapts an equalizer alternately by the algorithm with excellent blind convergence characteristics or the algorithm with better steady-state error performance. In this paper, it is introduced that the alternate adaptation equalization of the vsCMA (variable step-size CMA) and the decision-directed (DD) algorithm. We, first, designed the vsCMA with variable step-size to improve the steady-state error performance of the CMA, and combined it with the DD by alternate adaptation. As a result, it was mitigated that the sensitivity of performance fluctuation due to switching timing in CMA-DD switching method, and it was improved that the convergence speed and steady-state error performance of the CMA. Through computer simulations, under multipath channel condition, the usefulness of the proposed method was confirmed for 16-QAM.

• Transactions of the Korean hydrogen and new energy society
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• v.28 no.3
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• pp.287-294
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• 2017

EVs manufacturers typically target a range of 300 km on a fully charged battery. Many studies have been conducted to improve these disadvantages. As a results, the mileage of EVs is expected to increase significantly. However, as the distance traveled by EVs increases, current test method (SCT) have many difficulties. The biggest problem is that it takes a lot of time to test an EVs and greatly increases the error rate during the test period. In order to solve these problems, this paper discusses the fuel economy test method of EVs for energy efficiency and mileage. The comparison of test methods was achieved by chassis dynamometer test about EVs. These review of test methods are intended to both improve testing efficiency and provide a practical testing methodology that can be easily adapted to accommodate future testing enhancements. In conclusion, the results of MCT mode and SCT mode comparison show similar results within 3 %, confirming that the test method is appropriate. Also, as the CSCM distance becomes shorter in the MCT mode, the mileage becomes longer and the fuel economy becomes lower. As a result, the error from the SCT test results is expected to increase. In order to minimize the error of SCT measurement fuel economy, it is recommended to maximize the CSCM driving distance. However, since the timing of the EOT is not clearly known, it is reasonable to define the allowable range of the CSCE to be within 20 % of the MCT total mileage.

• International Journal of Aeronautical and Space Sciences
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• v.6 no.1
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• pp.44-51
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• 2005

To provide more accurate and reliable positioning and timing services to Korean nationwide users, the Ministry of Maritime Affairs and Fisheries of Korea is implementing Korean NDGPS (Nationwide DGPS), which is operational partly. And it also has a plan to construct WADGPS (Wide Area Differential GPS) system using sites and equipments of the NDGPS reference stations. For that, Seoul National University GNSS Laboratory is implementing and testing prototypes of WRS (Wide-area Reference Station) and WMS (Wide-area Master Station). Until now, because there are not enough installed WRSs to be used for computing wide area correction information, we cannot test algorithms of WMS with the data processed actually in WRSs. Therefore to evaluate the performance of the algorithms, we made a MATLAB program which can process RINEX (Receiver INdependent Exchange) format data with WADGPS algorithm. Using that program which consists of WRS, WMS and USER modules, we processed the data collected at NDGPS reference stations, which are saved in RINEX format. In WRS module, we eliminate the atmospheric delay error from the pseudorange measurement, smooth the measurement by hatch filter and calculate pseudorange corrections for each satellite. WMS module collects the processed data from each reference stations to generate the wide area correction information including estimated satellite ephemeris errors, ionospheric delays at each grid point, UDRE (User Differential Range Error), GIVE (Grid Ionosphere Vertical Error) and so on. In USER part, we use the measurements of reference stations as those of users and estimate the corrected users' positions and protection levels (HPL, VPL). With the results of estimation, we analyzed the performance of the algorithms. We assured the estimated UDRE /GIVE values and the protection levels bound the corresponding errors effectively. In this research, we can expect the possible performance of WADGPS in Korea, and the developed modules will be useful to implementation and improvement of the algorithms.