• 대한원격탐사학회:학술대회논문집
• /
• 대한원격탐사학회 2005년도 Proceedings of ISRS 2005
• /
• pp.637-640
• /
• 2005

In the development of a electronic system for a optical payload comprising mainly EOS(Electro-Optical Sub-system) and PDTS(Payload Data Transmission Sub-system), many aspects should be investigated and discussed for the easy implementation, for th e higher reliability of operation and for the effective ness in cost, size and weight as well as for the secure interface with components of a satellite bus, etc. As important aspects the interfaces between a satellite bus and a payload, and some design features of the CEU(Camera Electronics Unit) inside the payload are described in this paper. Interfaces between a satellite bus and a payload depend considerably on whether t he payload carries the PMU(Payload Management Un it), which functions as main controller of the Payload, or not. With the PMU inside the payload, EOS and PDTS control is performed through the PMU keep ing the least interfaces of control signals and primary power lines, while the EOS and PDTS control is performed directly by the satellite bus components using relatively many control signals when no PMU exists inside the payload. For the CEU design the output channel configurations of panchromatic and multi-spectral bands including the video image data inter face between EOS and PDTS are described conceptually. The timing information control which is also important and necessary to interpret the received image data is described.

• 한국산학기술학회논문지
• /
• 제13권9호
• /
• pp.3849-3855
• /
• 2012

본 논문은 스텝핑 모터를 이용하여 수동변속기 차량의 클러치를 자동으로 제어하기 위한 제어알고리즘 및 제어로직 구현 결과를 기술한 것이다. 기본제어 알고리즘은 차량의 통신데이터를 이용하여 운전자 의지를 파악하고 이에 따라 클러치 연결 혹은 해제 시점을 파악하여, 이에 따른 구동신호를 발생시키고 클러치의 위치 및 이동거리는 구동신호의 펄스 개수에 의하여 계산된다. 제어로직을 마이크로프로세서에 탑재하는 과정은 자동코드생성기법을 이용하였으며 이를 프로토 타입 제어기에 탑재하여 기본 성능시험을 실시하였다.

• Journal of Biosystems Engineering
• /
• 제26권6호
• /
• pp.535-544
• /
• 2001

This study developed a manipulator for robotic harvester to harvest cucumber. The manipulator was designed and built fur transferring an end-effecter from a fixed point to a specified cucumber. Its development involved the integration of a manipulating system with a PC compatible, DC motors, geared boxes, timing belts, and a motor controller board. Software, written in Quick basic. combined the functions of motor control with various circumstances. In order to move smoothly and rapidly the manipulator, it's shoulder link and elbow link were minimized by using rotational inertial moment without a motor and a geared box. After 30 replications of exercising the manipulator, it was concluded that the precision values of the X, Y and Z axes were less than 0.5mm, 7.25mm and 0.35mm, respectively. The precision data indicated the manipulator was not missing any steps fur the harvester to reach a target cucumber.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 2005년도 ICCAS
• /
• pp.2164-2169
• /
• 2005

SFFS(Solid Freeform Fabrication System) can quickly makes models and prototype parts from 3D computer-aided design (CAD) data. Three dimensional printing(3DP) is a kind of the solid freeform fabrication. The 3DP process slices the modeling data into the 50-200um along to z axis. And we pile the powder and make the manufactures. A manufacture is made by the SFFS has the precision of the 50um. Therefore the x-y table of SFFS to move a printhead must be the system that has a high speed and accuracy. So we proposed the SMCSPO algorithm for SFFS. The major contribution is the design of a robust observer for estimating the state and the perturbation of the timing belt system, which is combined with a robust controller. The control performance of the proposed algorithm is compared with PD control by the simulation and the experiment. The control algorithm of the SFFS is presented in the office environment. The system between control system and printhead for the SFFS is also integrated

• Journal of Advanced Marine Engineering and Technology
• /
• 제28권3호
• /
• pp.475-481
• /
• 2004

Recently it is strongly required on lower fuel consumption. lower exhaust emission, higher engine performance. and social demands in a spark ignition gasoline engine. In this study. the experimental engine used at test. it has been modified the lean burn gasoline engine. and used the programmable engine management system, and connected the controller circuit which is designed for the engine control. At the parametric study of the engine experiment, it has been controlled with fuel injection, ignition timing. swirl mode, equivalence ratio engine dynamometer load and speed as the important factors governing the engine performance adaptively. It has been found the combustion characteristics to overcome the hysteresis phenomena between normal and lean air-fuel mixing ranges. by mean of the look-up table set up the mapping values. at the optimum conditions during the engine operation. As the result, it is found that the strength of the swirl flow with the variation of engine speed and load is effective on combustion characteristics to reduce the bandwidth of the hysteresis regions. The results show that mass fraction burned and heat release rate pattern with crank angle are reduced much rather, and brake specific fuel consumption is also reduced simultaneously.

• 대한기계학회논문집A
• /
• 제24권9호
• /
• pp.2361-2370
• /
• 2000

The introduction of inexpensive cylinder pressure sensors provides new opportunities for precise engine control. This paper presents a control strategy of spark advance based upon cylinder pressure of spark ignition engines. A location of peak pressure(LPP) is the major parameter for controlling the spark timing, and also the UP is estimated, using a multi-layer feedforward neural network, which needs only five pressure sensor output voltage samples at -40˚, -20˚, 0˚, 20˚, 40˚ after top dead center. The neural network plays an important role in mitigating the A/D conversion load of an electronic engine controller by increasing the sampling interval from 10 crank angle(CA) to 20˚ CA. A proposed control algorithm does not need a sensor calibration and pegging(bias calculation) procedure because the neural network estimates the UP from the raw sensor output voltage. The estimated LPP can be regarded as a good index for combustion phasing, and can also be used as an MBT control parameter. The feasibility of this methodology is closely examined through steady and transient engine operations to control individual cylinder spark advance. The experimental results have revealed a favorable agreement of individual cylinder optimal combustion phasing.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제12권12호
• /
• pp.5654-5668
• /
• 2018

Driven by security and real-time demands of Internet of Things (IoT), the timing of fog computing and edge computing have gradually come into place. Gateways bear more nearby computing, storage, analysis and as an intelligent broker of the whole computing lifecycle in between local devices and the remote cloud. In fog computing, the edge broker requires X-aware capabilities that combines software programmability, stream processing, hardware optimization and various connectivity to deal with such as security, data abstraction, network latency, service classification and workload allocation strategy. The prosperous of Field Programmable Gate Array (FPGA) pushes the possibility of gateway capabilities further landed. In this paper, we propose a software-defined gateway (SDG) scheme for fog computing paradigm termed as Fog Computing Zero-Knowledge Gateway that strengthens data protection and resilience merits designed for industrial internet of things or highly privacy concerned hybrid cloud scenarios. It is a proxy for fog nodes and able to integrate with existing commodity gateways. The contribution is that it converts Privacy-Enhancing Technologies rules into provable statements without knowing original sensitive data and guarantees privacy rules applied to the sensitive data before being propagated while preventing potential leakage threats. Some logical functions can be offloaded to any programmable micro-controller embedded to achieve higher computing efficiency.

• 한국통신학회논문지
• /
• 제29권8C호
• /
• pp.1113-1124
• /
• 2004

본 논문에서는 입력 영상을 실시간으로 압축 및 복원할 수 있는 하드웨어(hardware, H/W)의 구조를 제안하고 처리되는 영상의 보안 및 보호를 위한 워터마킹 기법(watermarking)을 제안하여 H/W로 내장하고자 한다. 영상압축과 복원과정을 하나의 FPGA 칩 내에서 처리할 수 있도록 요구되는 모든 영상처리 요소를 고려하였고 VHDL(VHSIC Hardware Description Language)을 사용하여 각각을 효율적인 구조의 H/W로 사상하였다. 필터링과 양자화 과정을 거친 다음에 워터마킹을 수행하여 최소의 화질 감소를 가지고 양자화 과정에 의해 워터마크의 소실이 없으면서 실시간으로 동작이 가능하도록 하였다. 구현된 하드웨어는 크게 데이터 패스부(data path part)와 제어부(Main Controller, Memory Controller)로 구분되고 데이터 패스부는 영상처리 블록과 데이터처리 블록으로 나누어진다. H/W 구현을 위해 알고리즘의 기능적인 간략화를 고려하여 H/W의 구조에 반영하였다. 동작은 크게 영상의 압축과 복원과정으로 구분되고 영상의 압축 시 대기지연 시간 없이 워터마킹이 수행되며 전체 동작은 A/D 변환기에 동기하여 필드단위의 동작을 수행한다. 구현된 H/W는 APEX20KC EP20K600CB652-7 FPGA 칩에서 69%(16980개)의 LAB(Logic Array Block)와 9%(28352개)의 ESB(Embedded System Block)을 사용하였고 최대 약 82MHz의 클록주파수에서 안정적으로 동작할 수 있어 초당 67필드(33 프레임)의 영상에 대해 워터마킹과 압축을 실시간으로 수행할 수 있었다.

• 전자공학회논문지
• /
• 제49권9호
• /
• pp.251-258
• /
• 2012

SSD (Solid-state Drive), 더 나아가 SSS (Solid-state Storage System)와 같은 고성능 스토리지 요구 사항을 지원하기 위해 최근 낸드 플래시 메모리도 DRAM에서와 같이 SDR (Single Data Rate)에서 고속 DDR (Double Data Rate) 신호구조로 진화하고 있다. 이에 따라 PHY (Physical layer) 회로 기술을 적용하여 협소 타이밍 윈도우 내에서 유효 데이터를 안정적으로 래치하고, 핀 간 데이터 스큐를 최소화하는 것 등이 새로운 이슈로 부각되고 있다. 또한, 낸드 플래시 동작 속도의 증가는 낸드 플래시 컨트롤러의 동작 주파수 상승으로 이어지고 동작 모드에 따라 컨트롤러 내부 소모 전력 변동성이 급격히 증가한다. 공정 미세화와 저전력 요구에 의해 컨트롤러 내부 동작 전압이 1.5V 이하로 낮아지면서 낸드 플래시 컨트롤러 내부 전압 변화 마진폭도 좁아지므로 이러한 소모 전력 변동성 증가는 내부 회로의 정상 동작 범위를 제한한다. 컨트롤러의 전원전압 변동성은 미세공정으로 인한 OCV (On Chip Variation)의 영향이 증가함에 따라 더 심화되는 추세이고, 이러한 변동성의 증가는 순간적으로 컨트롤러의 보장된 정상 동작 범위를 벗어나게 되어 내부 로직의 오류를 초래한다. 이런 불량은 기능적 오류에 의한 것이 아니므로 문제의 원인 규명 및 해결이 매우 어렵게 된다. 본 논문에서는 낸드플래시 컨트롤러 내부의 비정상적 전원 전압 변동하에서도 유효 타이밍 윈도우를 경제적인 방법으로 유지할 수 있는 회로 구조를 제안하였다. 실험 결과 기존 PHY회로 대비 면적은 20% 감소한 반면 최대 데이터 스큐를 379% 감소시켜 동등한 효과를 보였다.

• 마이크로전자및패키징학회지
• /
• 제17권4호
• /
• pp.73-76
• /
• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.