• 한국통신학회논문지
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• 제34권1C호
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• pp.28-36
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• 2009

Hellman에 의해서 처음 제시된 TMTO (time memory trade-o런 암호 해독 방법은 블록 암호, 스트림 암호, 그리고 해쉬 함수와 같은 일반적인 암호 시스템에 광범위하게 적용된다. 이 논문에서는 TMTO 암호 해독 방법에서 선계산 단계에서 테이블을 저장하기 위해 필요한 저장 공간을 감소시킬 수 있는 방법을 제안한다. 시작점을 의사난수 수열군 통해서 생성하고 시작점의 실제 값 대신 난수 수열 군에서 몇 번째로 취한 값인지에 대한 색인을 저장하는 방식으로 시작점을 저장하기 위해 필요한 메모리 용량을 줄일 수 있다. 이 논문에서는 이 방법을 사용하면 키의 길이가 126 비트일 경우에 시작점을 저장하기 위해 필요한 메모리의 양을 10% 이하로 줄이는 것도 가능하다는 것을 보일 것이다. 이에 대한 비용으로 온라인 단계에서의 탐색 시간이 조금 더 늘어나지만 메모리가 시간에 비해서 더 비싼 자원이기 때문에 필요한 메모리 용량이 감소하게 되면 공격의 실현가능성이 더욱 커지게 된다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.44-57
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• 2016

Rectification is used as a preprocessing to reduce the computation complexity of disparity estimation. However, rectification also requires a complex computation. To minimize the computing complexity, rectification using a lookup-table (R-LUT) has been introduced. However, since, the R-LUT consumes large amount of memory, rectification with compressed LUT (R-CLUT) has been introduced. However, the more we reduce the memory consumption, the more we need decoding overhead. Therefore, we need to attain an acceptable trade-off between the size of LUT and decoding overhead. In this paper, we present such a trade-off by adaptively combining simple coding methods, such as differential coding, modified run-length coding (MRLE), and Huffman coding. Differential coding is applied to transform coordinate data into a differential form in order to further improve the coding efficiency along with Huffman coding for better stability and MRLE for better performance. Our experimental results verified that our coding scheme yields high performance with maintaining robustness. Our method showed about ranging from 1 % to 16 % lower average inverse of compression ratio than the existing methods. Moreover, we maintained low latency with tolerable hardware overhead for real-time implementation.

• 한국통신학회논문지
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• 제25권10B호
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• pp.1675-1689
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• 2000

We present CReMeS a CORBA-compliant design and implementation of a new real-time communication service. It provides for efficient predictable and scalable communication between information producers and consumers. The CReMeS architecture is based on MidART's Real-Time Channel-based Reflective Memory (RT-CRM) abstraction. This architecture supports the separation of QoS specification between producer and consumer of data and employs a user-level scheduling scheme for communicating real-time tasks. These help us achieve end-to-end predictability and allows our service to scale. The CReMeS architecture provides a CORBA interface to applications and demands no changes to the ORB layer and the language mapping layer. Thus it can run on non real-time Off-The-Shelf ORBs enables applications on these ORBs to have scalable and end-to-end predictable asynchronous communication facility. In addition an application designer can select whether to use an out-of-band channel or the ORB GIOP/IIOP for data communication. This permits a trade-off between performance predictability and reliability. Experimental results demonstrate that our architecture can achieve better performance and predictability than a real-time implementation of the CORBA Even Service when the out-of-band channel is employed for data communication it delivers better predictability with comparable performance when the ORB GIOP/IIOP is used.

• 한국통신학회논문지
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• 제25권10B호
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• pp.1648-1664
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• 2000

This paper proposes a real-time dynamic storage allocation algorithm QSHF(quick-segregated-half-fit) that provides various memory allocation policies. that manages a free block list per each word size for memory requests of small size good(segregated)-fit policy that manages a free list per proper range size for medium size requests and half-fit policy that manages a free list per proper range size for medium size requests and half-fit policy that manages a free list per each power of 2 size for large size requests. The proposed algorithm has the time complexit O(1) and makes us able to easily estimate the worst case execution time(WCET). This paper also suggests two algorithm that finds the proper free list for the requested memory size in predictable time and if the found list is empty then finds next available non-empty free list in fixed time. In order to confirm efficiency of the proposed algorithm we simulated the memory utilization of each memory allocation policy. The simulation result showed that each policy guarantees the constant WCET regardless of memory size but they have trade-off between memory utilization and list management overhead.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.257-258
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• 2006

In this paper, we address several issues in the real time implementation of MPEG-1 Layer II decoder on a fixed-point digital signal processor (DSP), especially TMS320C6416. There is a trade-off between processing speed and the size of program/data memory for the optimal implementation. In a view of the speed optimization, we first convert the floating point operations into fixed point ones with little degradation in audio quality, and then the look-up tables used for the inverse quantization of the audio codec are forced to be located into the internal memory of the DSP. And then, window functions and filter coefficients in the decoder are precalculated and stored as constant, which makes the decoder faster even larger memory size is required. It is shown from the real-time experiments that the fixed-point implementation enables us to make the decoder with a sampling rate of 48 kHz operate with 3 times faster than real-time on TMS320C6416 at a clock rate of 600 MHz.

• International journal of advanced smart convergence
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• 제12권2호
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• pp.117-126
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• 2023

To improve the overall performance and realism of your game, it is important to calculate the trajectory of a projectile accurately and quickly. One way to increase realism is to use a ballistic model that takes into account factors such as air resistance, density, and wind when calculating a projectile's trajectory. However, the more these factors are taken into account, the more computationally time-consuming and expensive it becomes, creating a trade-off between overall performance and efficiency. Therefore, we present an optimal solution to find a balance between ballistic model accuracy and computation time. We perform ballistic calculations using numerical methods such as Euler, Velocity Verlet, RK2, RK4, and Akima interpolation, and measure and compare the computation time, memory usage (RSS, Resident Set Size), and accuracy of each method. We show developers how to implement more accurate and efficient ballistic models and help them choose the right computational method for their numerical applications.

• 전자공학회논문지C
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• 제35C권2호
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• pp.36-47
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• 1998

Low power circuit techniques have been developed to realize the highest possible performance of embedded SRAM at 1V power supply with$0.5\mu\textrm{m}$ single threshold CMOS technology in which the unbalance between NMOS and PMOS threshold voltages is utilized to optimize the low power CMOS IC design. To achieve the best trade-off between the transistor drivability and the subthreshold current increase, the ground potential of memory array is raised to suppressthe subthreshold current. The problems of lower cellstability and bit-line dealy increase due to the enhanced array ground potential are evaluated to be controlled within the allowable range by careful circuit design. 160MHz, 128kb embedded SRAM with 3.4ns access time is demonstrated with the power consumption of 14.8mW in active $21.4{mu}W$ in standby mode at 1V power supply.

• 한국CDE학회논문집
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• 제13권1호
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• pp.1-7
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• 2008

Data compression becomes increasingly an important issue for reducing data storage spaces as well as transmis-sion time in network environments. In 3D geometric models, the normal vectors of faces or meshes take a major portion of the data so that the compression of the vectors, which involves the trade off between the distortion of the images and compression ratios, plays a key role in reducing the size of the models. So, raising the compression ratio when the normal vector is compressed and minimizing the visual distortion of shape model's shading after compression are important. According to the recent papers, normal vector compression is useful to heighten com-pression ratio and to improve memory efficiency. But, the study about distortion of shading when the normal vector is compressed is rare relatively. In this paper, new normal vector compression method which is clustering normal vectors and assigning Representative Normal Vector (RNV) to each cluster and using the angular deviation from actual normal vector is proposed. And, using this new method, Visually Undistinguishable Lossy Compression (VULC) algorithm which distortion of shape model's shading by angular deviation of normal vector cannot be identified visually has been developed. And, being applied to the complicated shape models, this algorithm gave a good effectiveness.

• 정보과학회 논문지
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• 제42권6호
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• pp.691-698
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• 2015

응용프로그램의 기동 시간은 기기에 대한 사용자 체험에 영향을 주는 중요한 지표로 보조 기억 장치의 성능에 의해 큰 영향을 받는다. 하드디스크 대신 SSD를 사용하게 되면 기동 시간을 크게 낮출 수 있지만 비용 대비 성능을 고려하면 작은 용량의 SSD를 하드디스크의 캐시로 쓰는 것이 현실적인 대안이 될 수 있다. 본 논문에서는 파일시스템 수준에서 하드디스크 상의 블록을 SSD로 이주시키는 기법을 제안한다. 제안한 기법은 기존의 SSD 캐싱 기법들에서 요구되던 캐시 데이터의 사상에 필요한 주 메모리, CPU, 그리고 사상 정보의 유지를 위한 SSD 공간 사용의 부가적인 오버헤드가 없다. 8개의 응용프로그램을 이용한 실험에서 메타데이터와 데이터 블록을 모두 SSD에 캐싱한 경우에 기동시간이 평균 56% 단축됨을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.8-22
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• 2014

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted silicon-on-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmented-channel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.