• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.22-28
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• 2009

This paper presents a fast received signal strength indicator (RSSI) circuit for wireless communication application. The proposed circuit is developed using power detectors and an analog-to-digital converter to achieve a fast settling time. The power detector is consisted of a novel logarithmic variable gain amplifier (VGA), a peak detector, and a comparator in a closed loop. The VGA achieved a wide logarithmic gain range in a closed loop form for stable operation. For the peak detector, a fast settling time and small ripple are obtained using the orthogonal characteristics of quadrature signals. In $0.18-{\mu}m$ CMOS process, the RSSI value settles down in $20{\mu}s$ with power consumption of 20 mW, and the maximum ripple of the RSSI is 30 mV. The proposed RSSI circuit is fabricated with a personal handy-phone system transceiver. The active area is $0.8{\times}0.2\;mm^2$.

• Journal of Power Electronics
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• v.15 no.1
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• pp.10-17
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• 2015

A quasi-constant on-time controlled buck front end in combined discontinuous conduction mode and boundary conduction mode is proposed to improve power factor (PF).When instantaneous AC input voltage is lower than the output bus voltage per period, the buck converter turns into buck-boost converter with the addition of a level comparator to compare input voltage and output voltage. The gate drive voltage is provided by an additional oscillator during distortion time to eliminate the cross-over distortion of the input current. This high PF comes from the avoidance of the input current distortion, thereby enabling energy to be delivered constantly. This paper presents a series analysis of controlling techniques and efficiency, PF, and total harmonic distortion. A comparison in terms of efficiency and PF between the proposed converter and a previous work is performed. The specifications of the converter include the following: input AC voltage is from 90V to 264V, output DC voltage is 80V, and output power is 94W.This converter can achieve PF of 98.74% and efficiency of 97.21% in 220V AC input voltage process.

• Smart Media Journal
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• v.5 no.3
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• pp.49-53
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• 2016

Related researches are progressing that method of non-contact method using the electromagnetic field on the human body by detecting the motion recognition signal is the limitations of time and space, so less than the existing systems. In this paper, we designed the circuit system that can implement the hardware that can detect the electric field signal of the human body non-contact method to increase the recognition rate to screen this digital waveform. The PCB design Used to automatically increase of composition of the circuit and the linkage of the comparator digital waveform with circuit simulation of the system. At same time for evaluate the characteristics of the whole circuit system.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• Journal of Digital Convergence
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• v.16 no.12
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• pp.309-315
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• 2018

In this paper, propose an efficient arc detection and control method to achieve fast machining speed, improved precision and surface roughness in discharge machining, especially for carbide and hard material processing and metal processing using discharge phenomenon as energy. A single discharge waveform is divided into three sections of Td (Time-Delay), Ton (Time-on) and Toff (Time-off) and the gate control timing is simulated using the HDL language. In this paper, we analyze the effect of the gap between the electrode and the workpiece on the machining results by determining the operation of the servo mechanism by sampling the Td section through the comparator circuit. As a result of the analysis, the Td section of the formed waveform was more precisely sampled at a high speed and the results were improved when applied to the gap control between the electrode and the workpiece.

• Journal of the Korean Society of Industry Convergence
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• v.25 no.3
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• pp.423-431
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• 2022

The UPS(Uninterruptible Power Supply) system operates in the battery charging mode when the grid is normal, and in the UPS mode, which is the battery discharge mode when a grid error occurs. Since the UPS must supply the same voltage as the grid to the load within 4 [ms] in case of a grid error, the switching time and power recovery time should be short when controlling the output voltage and current of the UPS, and the power failure detection time is also important. The power outage detection algorithm using DFT(Discrete Fourier Transform) proposed in this paper compares the grid voltage waveform with the voltage waveform including the 9th harmonic generated through DFT using Schmitt trigger to detect power outage faster than the existing power outage monitoring algorithm. There are advantages. Therefore, it is possible to supply instant and stable power when switching modes in the UPS system. The multi-power-applied UPS system proposed in this paper uses DFT, which is faster than the conventional blackout monitoring algorithm in detecting power failure, to provide stable power to the load in a shorter time than the existing power outage monitoring algorithm when a system error occurs. The detection method was applied. The changeover time of mode switching was set to less than 4 [ms], which is 1/4 of the system cycle, in accordance with KSC 4310 regulation, which was established by the Industrial Standards Council on the regulation of uninterruptible power supply. A 10 [kW] UPS system in which commercial voltage, vehicle generator, and auxiliary diesel generator can be connected to each of the proposed transfer devices was constructed and the feasibility was verified by conducting an experiment.

• Publications of The Korean Astronomical Society
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• v.22 no.4
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• pp.189-199
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• 2007

In this paper, we describe the proposed KVN (Korean VLBI Network) clock system in order to make the observation of the VLBI effectively. In general, the GPS system is widely used for the time information in the single dish observation. In the case of VLBI observation, a very high precise frequency standard is needed to perform the observation in accordance with the observation frequency using the radio telescope with over 100km distance. The objective of the high precise clock system is to insert the time-tagging information to the observed data and to synchronize it with the same clock in overall equipments which used in station. The AHM (Active Hydrogen Maser) and clock system are basically used as a frequency standard equipments at VLBI station. This system is also adopted in KVN. The proposed KVN clock system at each station consists of the AHM, GPS time comparator, standard clock system, time distributor, and frequency standard distributor. The basic experiments were performed to check the AHM system specification and to verify the effectiveness of implemented KVN clock system. In this paper, we briefly introduce the KVN clock system configuration and experimental results.

• Proceedings of the KSR Conference
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• 2011.05a
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• pp.1195-1201
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• 2011

Since the release of safety standard IEC 61508 which defines functional safety of electronic safety-related systems, SIL(Safety Integrity Level) certification for railway systems has gained lots of attention lately. In this paper, we propose a new design technique of the computer board for train control systems with high reliability and safety. The board is designed with TMR(Triple Modular Redundancy) using a certified SIL3 Texas Instrument(TI)'s TMS570 MCU(Micro-Controller Unit) to guarantee safety and reliability. TMR for the control device is implemented on FPGA(Field Programmable Gate Array) which integrates a comparator, a CAN(Controller Area Network) communication module, built-in self-error checking, error discriminant function to improve the reliability of the board. Even if a malfunction of a processing module occurs, the safety control function based on the proposed technique lets the system operate properly by detecting and masking the malfunction. An RTOS (Real Time Operation System) called FreeRTOS is ported on the board so that reliable and stable operation and convenient software development can be provided.

• Proceedings of the KIEE Conference
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• 1987.11a
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• pp.454-456
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• 1987

A more specialized area of transient evaluations is transmission line fault-detecting and protection system. During the first cycle or two following a power system fault, a high-speed protective relay is expected to make a decision as to the severity or location of the fault, usually based on 60 Hz information, i.e. the phase and magnitude of 60 Hz voltage or current signals. It is precisely at this time however that the signal is badly corrupted by noise, in the form of a de offset or frequencies above 50 Hz. One of several possible sources of transients in protection measuring signals is in the primary system for which protection is required in its response to the impact of short circuit fault on-set. Other sources are in the primary voltage and current transducers from which protection signals are derived, and, often of particular importance, in the interface circuits between the transducer secondaries and the comparator and measuring elements of the protection system. However, the noise signals that will be described in this paper are due to the main power system only and do not include errors due to current or voltage transducers.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.2
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• pp.33-44
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• 2010

This paper propose the structure of real-time face detection hardware architecture for robot vision processing applications. The proposed architecture is robust against illumination changes and operates at no less than 60 frames per second. It uses Modified Census Transform to obtain face characteristics robust against illumination changes. And the AdaBoost algorithm is adopted to learn and generate the characteristics of the face data, and finally detected the face using this data. This paper describes the face detection hardware structure composed of Memory Interface, Image Scaler, MCT Generator, Candidate Detector, Confidence Comparator, Position Resizer, Data Grouper, and Detected Result Display, and verification Result of Hardware Implementation with using Virtex5 LX330 FPGA of Xilinx. Verification result with using the images from a camera showed that maximum 32 faces per one frame can be detected at the speed of maximum 149 frame per second.