• Molecules and Cells
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• v.22 no.3
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• pp.285-290
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• 2006

The light sensing system in the eye directly affects the circadian oscillator in the mammalian suprachiasmatic nucleus (SCN). To investigate this relationship in the rat, we examined the circadian expression of clock genes in the SCN and eye tissue during a 24 h day/night cycle. In the SCN, rPer1 and rPer2 mRNAs were expressed in a clear circadian rhythm like rCry1 and rCry2 mRNAs, whereas the level of BMAL1 and CLOCK mRNAs decreased during the day and increased during the night with a relatively low amplitude. It seems that the clock genes of the SCN may function in response to a master clock oscillation in the rat. In the eye, the rCry1 and rCry2 were expressed in a circadian rhythm with an increase during subjective day and a decrease during subjective night. However, the expression of Opn4 mRNA did not exhibit a clear circadian pattern, although its expression was higher in daytime than at night. This suggests that cryptochromes located in the eye, rather than melanopsin, are the major photoreceptive system for synchronizing the circadian rhythm of the SCN in the rat.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.3
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• pp.264-274
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• 2014

Time synchronization becomes a critical issue in underwater acoustic networks (UANets) because nodes cooperate together or individually work by communicating each other in diverse underwater applications. Compared with the time synchronization approaches in terrestrial networks, several intrinsic limitations of UANets (e.g., the unavailability of GPS, long propagation delay, mobility due to currents, limited energy consumption, or low data rate) need to be considered in synchronizing the timing among underwater nodes. For the purpose of developing more efficient time synchronization protocols for UANets, we review the existing approaches, which estimate both the clock offset and the clock skew of underwater nodes. Finally, we outline the state-of-the art time synchronization protocols for UANets by comparing and summarizing them according to their synchronization characteristics.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.281-284
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• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.733-736
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• 1999

In this Paper, Bit selectable and Bi-directional Interface Port is described, which can communicate data with the peripheral devices. Specially A description of the asynchronous design method is given to remove the clock skew phenomenon and the output asynchronous control method which finds the optimal clock and controls all the enable signal of the output pins at the same time is presented. Using this technique interface ports have delay time of less-than 0.5㎱.

• The Journal of the Korea Contents Association
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• v.12 no.5
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• pp.62-69
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• 2012

The newly developed field of media art is quickly making progress to include various and up-to-date forms of expression. Unlike in traditional art, the communication between the art and the viewer has become vastly important, in which the viewer is an active agent who participates and interacts with the artwork. These digital artworks can now be readily observed in everyday places and things, rather than being confined solely in the gallery space. By encouraging open interaction with the public, media art has become more accessible. Accordingly, this thesis examines the construction of a real-time multimedia clock piece using particle systems. Time has always been a significant theme in the realm of traditional art, which continues to be explored extensively in various forms of expression. In an attempt to express the continuity of time and the state of being value of existence based on technological skills, the thesis presents an artwork that uses the popular medium of a clock while also providing both usability and emotional satisfaction for the viewer's sensibility through interaction.

• Journal of Institute of Control, Robotics and Systems
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• v.21 no.7
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• pp.669-676
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• 2015

In this paper, we described the simulation results of the phase offset performance of a clock in holdover mode which was normally operated in GPS Disciplined Oscillator (GPSDO). In the TIE model, we included the time error term caused by environmental temperature variation because one of the most important parameters of clock phase error is the frequency offset and drift caused by the variation of temperature. For the simulation, we employed Maximum Time Interval Error (MTIE) for the performance evaluation when the frequency offset and drift are estimated by using an Unbiased Finite Impulse Response (UFIR) filter with ladder algorithm. We assumed that the noise in the GPS measurement is white Gaussian with zero mean and 1 ns standard deviation, and temperature linearly varies with a slope of $1{^{\circ}C}$ per hour. From the simulation results, the followings were observed. First, with the estimation error of temperature of less than 3 % and the temperature compensation period of less than 900 seconds, the requirement of CDMA2000 phase synchronization under 10 us could be achieved for more than 40,000 seconds holdover time if we employ an OCXO (Oven Controlled Crystal Oscillator) clock. Second, in order to achieve the requirement of LTE-TDD under 1.5 us for more than 10,000 seconds holdover time, below 3 % estimation error and 500 seconds should be retained if a Rubidium clock is adopted.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.625-631
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• 2014

We propose a compact power-on reset circuit consisting of a switched capacitor, a capacitor, and a Schmitt trigger inverter. A switched capacitor working with a clock signal charges the capacitor. Thus, the voltage across the capacitor is increased toward the supply voltage. The circuit provides a reset pulse until the voltage across the capacitor reaches the high threshold voltage of the Schmitt trigger inverter. The proposed circuit is simple, compact, has no static power consumption, and works for a wide range of power-on rising times. Furthermore, the clock signal is available while the reset pulse is activated. The proposed circuit works for up to 6 s of power-on rising time, and occupies a $60{\times}30{\mu}m^2$ active area.

• The KIPS Transactions:PartC
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• v.16C no.1
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• pp.51-56
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• 2009

Time synchronization algorithm in wireless sensor networks is essential to various applications such as object tracking, data encryption, duplicate detection, and precise TDMA scheduling. This paper describes CDRS that is a time synchronization algorithm using the Clock Drift rate and Reference Signals between two sensor nodes. CDRS is composed of two steps. At first step, the time correction is calculated using offset and the clock drift rate between the two nodes based on the LTS method. Two nodes become a synchronized state and the time variance can be compensated by the clock drift rate. At second step, the synchronization node transmits reference signals periodically. This reference signals are used to calculate the time difference between nodes. When this value exceeds the maximum error tolerance, the first step is performed again for resynchronization. The simulation results on the performance analysis show that the time accuracy of the proposed algorithm is improved, and the energy consumption is reduced 2.5 times compared to the time synchronization algorithm with only LTS, because CDRS reduces the number of message about 50% compared to LTS and reference signals do not use the data space for timestamp.

• Journal of Positioning, Navigation, and Timing
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• v.9 no.4
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• pp.397-403
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• 2020

In order to synchronize a remote system time to the reference time like Coordinated Universal Time (UTC), it is required to compare the time difference between the two clocks. The time comparison data may have some outliers and the time synchronization performance can be significantly degraded if the outliers are not removed. Therefore, it is required to employ an effective outlier detection algorithm for keeping high accurate system time. In this paper, an outlier detection method is presented for the time difference data of GNSS time transfer receivers. The time difference data between the system time and the GNSS usually have slopes because the remote system clock is under free running until synchronized to the reference clock time. For investigating the outlier detection performance of the proposed algorithm, simulations are performed by using the time difference data of a GNSS time transfer receiver corrected to a free running Cesium clock with intentionally inserted outliers. From the simulation, it is investigated that the proposed algorithm can effectively detect the inserted outliers while conventional methods such as modified Z-score and adjusted boxplot cannot. Furthermore, it is also observed that the synchronization performance can be degraded to more than 15% with 20 outliers compared to that of original data without outliers.

• Journal of the Korea Institute of Military Science and Technology
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• v.23 no.5
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• pp.516-522
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• 2020

In this paper, the frequency detector which detects the clock frequency of the embedded system is proposed and analyzed. The proposed frequency detector is consisted of filter and peak voltage detector. The clock signal is converted from square wave to triangular wave by the filter. The peak voltage of the triangular wave is determined according to the frequency response of filter. The peak voltage detector detects and holds the peak voltage of the signal. Moreover, the proposed clock frequency detector can detect the frequency within 1ms and it gives guarantee of real-time operation.