• 대한임베디드공학회논문지
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• 제12권3호
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• pp.169-176
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• 2017

To replace conventional DRAM, many researches have been done on nonvolatile memories. The DRAM&PCM hybrid memory is one of the effective structure because it can utilize an advantage of DRAM and PCM. However, in order to use this characteristics, pages can be replaced frequently between DRAM and PCM. Therefore, PCM still has major problem that has write-limits. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an average access time and write count of PCM by utilizing two locality for an effective page replacement. We proposed a page selection algorithm which is recently requested to write in DRAM and an algorithm witch uses two locality in PCM. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM write count by around 22% and the average access time by 31% given the same PCM size, compared with CLOCK-DWF algorithm.

• 전자공학회논문지SC
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• 제39권4호
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• pp.36-42
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• 2002

본 논문에서는 유한체 GF($P^m$)상에서 모든 항의 계수가 이 아닌 두 다항식의 승산 알고리즘을 제시하였다. 제시된 승산 알고리즘을 이용하여 모듈 구조의 병렬 입-출력 승산기를 구성하였다. 제시된 승산기는 $(m+1)^2$개의 동일한 셀로 구성되었으며, 각각의 셀은 1개의 mod(p) 가산 게이트와 1개의 mod(p) 승산 게이트로 구성되었다. 본 논문에서 제시된 승산기는 클럭이 필요하지 않고 m개의 mod(p) 가산 게이트 지연시간과 1개의 mod(p) 승산 게이트 소자 지연시간만을 필요로 한다. 또한, 제시된 승산기는 규칙성과 셀 배열에 의한 모듈성을 가지므로 VLSI 회로 실현에 적합할 것이다.

• 대한전자공학회논문지TC
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• 제37권1호
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• pp.88-97
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• 2000

초고속이면서 소요 메모리의 크기를 극소화한 IP 라우터용 Lookup 알고리즘을 제안하고 성능을 분석하였다. 메모리 크기가 작으므로 고속/고가의 SRAM(10ns)을 사용할 수 있고, 구조가 간단하여 하드웨어로 구현 가능하였다. 본 장치는 1${\sim}$3회의 메모리 접근을 통해 Lookup이 가능하고, IPMA 사이트에서 구한 40,000개의 라우팅 정보를 이용하여 시뮬레이션한 결과 대략 ${\sim}$316KB의 포워딩 테이블용 메모리만이 소요된다. 이때 압축을 수행하는 옵셋 임계치는 8이다. ALTERA EPM7256시리즈에 100MHz 클럭을 이용하여 모사시험한 결과 10ns 접근속도를 가진 SRAM 기준으로 2회의 메모리 접근만으로 Lookup하는 경우 45ns의 접근시간이 소요되며, 3회의 메모리 접근이 필요한 경우는 ${\sim}$177ns의 접근시간이 소요된다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.430-442
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• 2013

This paper presents a fast multi-reference frame integer motion estimator for H.264/AVC. The proposed system uses the previously proposed fast multi-reference frame algorithm. The previously proposed algorithm executes a full search area motion estimation in reference frames 0 and 1. After that, the search areas of motion estimation in reference frames 2, 3 and 4 are minimized by a linear relationship between the motion vector and the distances from the current frame to the reference frames. For hardware implementation, the modified algorithm optimizes the search area, reduces the overlapping search area and modifies a division equation. Because the search area is reduced, the amount of computation is reduced by 58.7%. In experimental results, the modified algorithm shows an increase of bit-rate in 0.36% when compared with the five reference frame standard. The pipeline structure and the memory controller are also adopted for real-time video encoding. The proposed system is implemented using 0.13 um CMOS technology, and the gate count is 1089K with 6.50 KB of internal SRAM. It can encode a Full HD video ($1920{\times}1080P@30Hz$) in real-time at a 135 MHz clock speed with 5 reference frames.

• 대한전자공학회논문지TE
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• 제37권3호
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• pp.37-44
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• 2000

본 논문에서는 실시간 데이터 압축을 위한 Lempel-Ziv 압축기의 효과적인 하드웨어 구조를 제안한다. 일반적으로 Lempel-Ziv 알고리즘의 구현에서는 matching 바이트 탐색과 dictionary 버퍼의 누적된 shift 동작이 처리 속도에 가장 중요한 문제이다. 제안하는 구조에서는 dictionary 크기를 최적화하는 방법과 복수개의 바이트를 동시에 비교하는 matching 바이트 처리 방법, 그리고 회전 FIEO 구조를 이용하여 shift 동작 제어 방법을 이용함으로써 효과적인 Lempel-Ziv 알고리즘의 처리 구조를 제안하였다. 제안된 구조는 상용 DSP를 사용하여 하드웨어적으로 정확하게 동작함을 검증하였으며, VHDL로 기술한 후 회로 합성을 수행하여 상용 FPGA 칩에 구현하였다. 제안된 구조는 시스템 클락 33㎒, 비트율 256Kbps 전용선에서 오류 없이 동작함을 확인하였다.

• 수산해양기술연구
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• 제24권1호
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• pp.1-6
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• 1988

For the purpose of making the detection range of fish detection system more longer and computerizing the system a parametric sound source, a timer and a digitizing circuit for the Apple II computer have been studied. The parametric sound of 5 KHz generated by passing AND gate two signals from carrier signal generator of 200KHz with modulator of 5KHz. This parametric acoustic source of 5KHz difference frequency had more higher directional resolution of 10 degrees than single frequency sound of 200KHz. Peripheral interface adaptor MC 6821 was adopted for interfacing to the Apple II personal computer. The timer consisted of six decade binary coded decimal counters (74 LS 190), and the digitizing circuit consisted of a sample and hold (LF 398) and an A/D converter(ADC 0808). The timer with 10KHz clock pulse had the measuring time from 0.1msec to 100sec. This time measuring range was satisfactory for the aim of the fish finding acoustic system.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제9권8호
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• pp.3103-3120
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• 2015

This paper presents a single-phase energy metering chip with built-in calibration function to measure electric power quantities. The entire chip consists of an analog front end, a filter block, a computation engine, a calibration engine, and an external interface block. The key design issues are how to reduce the implementation costs of the computation engine from repeatedly used arithmetic operations and how to simplify calibration procedure and reduce calibration time. The proposed energy metering chip simplifies the computation engine using time-division multiplexed arithmetic units. It also provides a simple and fast calibration scheme by using integrated digital calibration functionality. The chip is fabricated with 0.18-μm six-layer metal CMOS process and housed in a 32-pin quad-flat no-leads (QFN) package. It operates at a clock speed of 4096 kHz and consumes 9.84 mW in 3.3 V supply.

• 천문학회보
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• 제41권1호
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• pp.61.3-62
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• 2016

An asteroid family is a group of asteroidal objects in the proper orbital element space (a, e, and i), considered to have been produced by a disruption of a large parent body through a catastrophic collision. Family members usually have similar surface properties such as spectral taxonomy types, colors, and visible geometric albedo with a same dynamical age. Therefore an asteroid family could be called as a natural Solar System laboratory and is also regarded as a powerful tool to investigate space weathering and non-gravitational phenomena such as the Yarkovsky/YORP effects. We carry out time series photometric observations for a number of asteroid families to obtain their physical properties, including sizes, shapes, rotational periods, spin axes, colors, and H-G parameters based on nearly round-the-clock observations, using several 0.5-2 meter class telescopes in the Northern hemisphere, including BOAO 1.8 m, LOAO 1.0 m, SOAO 0.6 m facilities in KASI, McDonald Observatory 2.1 m instrument, NARIT 2.4 m and TUG 1.0 m telescopes. This study is expected to find, for the first time, some important clues on the collisional history in our Solar System and the mechanisms where the family members are being transported from the resonance regions in the Main-belt to the near Earth space.

• 한국통신학회논문지
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• 제10권3호
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• pp.115-122
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• 1985

本 論文에서는 (7, 4) 循環코드와 (3, 1) 循環 코드의 곱의 디코더가, 같은 코드를 使用하는 보통의 다른 두 段階 多數決 理論 디코더에 비해서, 적은 수의 多數決 게이트들을 使用하도록 設計되었고, 多數決 게이트로서 ROM(read only memory)을 使用한 結果로 디코더는 간단한 構造로 製作되었다. 한 개의 受信語(혹은 21bits)을 完全히 安定시키는데 42개의 클럭 펄스가 經過하였다. 그래서 이 디코딩은 두 개의 디코더들과 二次元 語의 配列을 함께 使用한 從來의 디코딩에 비해서 디코딩 時間이 약 0.7배가 되었다.

• Journal of Communications and Networks
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• 제18권2호
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• pp.201-209
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• 2016

In wireless sensor networks (WSNs) duty cycling has been an imperative choice to reduce idle listening but it introduces sleep delay. Thus, the conventional WSN medium access control protocols are bound by the energy-latency tradeoff. To break through the tradeoff, we propose a radio wave sensor called radio frequency (RF) wakeup sensor that is dedicated to sense the presence of a RF signal. The distinctive feature of our design is that the RF wakeup sensor can provide the same sensitivity but with two orders of magnitude less energy than the underlying RF module. With RF wakeup sensor a sensor node no longer requires duty cycling. Instead, it can maintain a sleep state until its RF wakeup sensor detects a communication signal. According to our analysis, the response time of the RF wakeup sensor is much shorter than the minimum transmission time of a typical communication module. Therefore, we apply duty cycling to the RF wakeup sensor to further reduce the energy consumption without performance degradation. We evaluate the circuital characteristics of our RF wakeup sensor design by using Advanced Design System 2009 simulator. The results show that RF wakeup sensor allows a sensor node to completely turn off their communication module by performing the around-the-clock carrier sensing while it consumes only 0.07% energy of an idle communication module.