• 전기의세계
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• 제25권5호
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• pp.59-62
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• 1976

Applications of the digital computers in the control systems are not new. But when one tries to integrate the control system with a digital computer to form a feedback loop, he has to solve a great deal of problems in both hardware and software aspects. Such problems are investigated in this paper. For the hardware aspect, one has to design interfaces for both ADC and DAC. Since these are absolutely necessary pieces of hardware, one can notavoid from using them. The interface which employ the programmed data transfer method was designed for this research. For the software aspect, one has to build models for the digital compensator and the controlled system. In order to do that it is necessary to utilize the real time clock and to write his own interrupt service routine. As a sample case, a deadbeat compensator was desinged and tested.

• 한국산업정보학회논문지
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• 제7권3호
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• pp.1-8
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• 2002

GF(2$^{m}$ )상에서 모듈러 곱셈은 공개키 암호 시스템과 같은 응용에서의 기본 연산으로 사용된다. 본 논문에서는 이와 같은 모듈러 곱셈 연산을 셀룰러 오토마타를 이용하여, GF(2$^{m}$ )상에서 m클럭 사이클만에 처리할 수 있는 연산기를 설계하였다. 이 곱셈기는 LSB 우선 방식으로 설계되었으며, 기존의 시스톨릭 구조를 이용한 곱셈기 보다 하드웨어 복잡도가 낮고 처리 시간이 빠른 장점이 있다. 그리고 설계된 곱셈기는 지수연산을 위한 하드웨어 설계에 효율적으로 이용될 수 있을 것이다.

• 전기학회논문지P
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• 제62권2호
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• pp.84-89
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• 2013

In this paper, we propose interface circuits for reducing power consumption and EMI when sequences of data from LCD controller to LCD driver IC by transmitting two bit data during one clock period. The proposed circuits are operated in current mode, which is different from conventional voltage-mode signaling techniques, and also employ threshold technique of Modified-LVDS(Low Voltage Differential Signaling) method. We have simulated the proposed circuits using H-SPICE tool for performance analysis of the proposed method. The simulation results show that the proposed circuits provide a faster transmission speed and stronger noise immunity than the conventional LVDS circuits. It might be suitable for the real-time transmission of huge image data in LCD system.

• 정보처리학회지
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• 제5권5호
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• pp.99-110
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• 1998

인류의 역사는 앞으로 400여일이 지나면 새로운 천년을 맞이하게 된다 세계는 2000년을 기점으로 도약하기 위하여 VISION 2000을 제시하는 등 세기말을 바쁘게 지내고 있다 그러나 희망으로 다가오는 2000년은 시한폭탄이 되어 다가오고 이다 그것은 산업사회에서 정보화 사회로 이전되면서 우리가 모르는 사이에 디지털 시대에 살게 되었기 때문이다 디지털의 세계에서는 메모린의 절약과 표현의 간소화를 위하여 연도표기를 마지막 2자리 숫자로 사용하여왔다 그로인해 2000년이 되면 컴퓨터에서 처리되는 연도가 '00'으로 되어 1900년과 구별되지 않게 되었다 은행거래 각종공과금 계산의 오류는 물론이고 산업계 전역에 설치되어 있는 자동화기기의 RTC(Real Time Clock)오동작으로 국가 기반시스템까지 마비될 가능성을 파생시켰다 이러한 Y2K 문제(일명: 밀레니엄버그)는 크게 하드웨어 시스템 소프트웨어 애플리케이션 비정보처리계시스템(자동화기기)등 4가지 종류에서 발생하고 있다 본고에서는 이들 4가지 종류에 맞는 해결안을 마련하고 실현하는 구체적인 계획을 제시함을 물론 이어 최정적으로 이를 다시 통합해서 테스트하는 3단계방식으로 Y2K 문제를 해결하도록 제안하고자 한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.684_685
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• 2009

A digital sampling algorithm that uses a two high resolution integrating Voltmeters which are synchronized by Phase Lock Loop (PLL) time clock for accurately measuring the parameters, active and reactive power, for sinusoidal power measurements is presented. The PLL technique provides high precision measurements, root mean square (rms), phase and complex voltage ratio, of the AC signal. The system has been designed to be used at the Korean Research Institute of Standards and Science (KRISS) as a reference power standard for electrical power calibrations. The test results have shown that the accuracy of the measurements is better than $10 {\mu}W/VA$ and the level of uncertainty is valid for the power factor range zero to 1 for both lead and lag conditions. The system is fully automated and allows power measurements and calibration of high precision wattmeters and power calibrators at the main power frequencies 50 and 60 Hz.

• Journal of Biosystems Engineering
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• 제11권1호
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• pp.24-30
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• 1986

In order to collect the engine performance data accurately, rapidly and reliabily, the microcomputer-based engine performance test system was developed and tested. The system measures engine shaft torque and speed, fuel consumption, exhaust gas temperature, engine shaft power and fuel consumption ratio. The system consisted of 32 channels 8 bit A/D converter, time clock, dynamic strain amplifier and signal conditioning circuits to amplify and filter the electrical signal from transducers. Most of transducers were devised for low cost, easy setting and self-manufacturing. The system has been installed on a small kerosene engine (DAEDONG NA50B).

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1449-1453
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• 1987

A microprogrammable Bit Slice Sinal Processor for image processing is implemented. Processing speed is increased by the parallelism in horizontal microprogram using 120bits microcode, pipelined architecture, 2 bank memory switching that interfaces with the Host through DMA, a variable clock control, overflow checking H/W,look-up table method and cache memory. With this processor, a DCT algorithm which uses 2-D FFT is performed. The execution time for $512{\times}512{\times}8$ image is 12 sec when 16 bit operation is runned, and the recovered image has acceptable quality with MSE 0.276%.

• 국제초고층학회논문집
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• 제1권1호
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• pp.53-59
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• 2012

With the rise in CPU power and the generalization and popularity of computers, engineering practice also changed from hand calculations to 3D computer models, from elastic linear analysis to 3D nonlinear static analysis and 3D nonlinear transient dynamic analysis. Thanks to holistic design approach and current trends in freeform and contemporary architecture, BIM concept is no longer a dream but also a reality. BIM is not just providing a media for better co-ordination but also to shorten the round-the-clock time in updating models to match with other professional disciplines. With the parametric modeling tools, structural information is also linked with BIM system and quickly produces analysis and design results from checking to fabrication. This paper presents a new framework which not just linked the BIM system by means of parametric mean but also create and produce connection FE model and fabrication drawings etc. This framework will facilitate structural engineers to produce well co-ordinate, optimized and safe structures.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.118-125
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• 2016

This paper presents a new high-efficient algorithm and architecture for an elliptic curve cryptographic processor. To reduce the computational complexity, novel modified Lopez-Dahab scalar point multiplication and left-to-right algorithms are proposed for point multiplication operation. Moreover, bit-serial Galois-field multiplication is used in order to decrease hardware complexity. The field multiplication operations are performed in parallel to improve system latency. As a result, our approach can reduce hardware costs, while the total time required for point multiplication is kept to a reasonable amount. The results on a Xilinx Virtex-5, Virtex-7 FPGAs and VLSI implementation show that the proposed architecture has less hardware complexity, number of clock cycles and higher efficiency than the previous works.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1988년도 한국자동제어학술회의논문집(국내학술편); 한국전력공사연수원, 서울; 21-22 Oct. 1988
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• pp.414-417
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• 1988

Recently PLC pursues faster scanning time, circuit confidence, reliability improvement, and smaller size. To obtain above all merit, custom IC(Gate Array) is developed. Custom IC includes 5 main blocks and 2 auxiliary blocks. The 5 main blocks process faster sequential instruction execution by only logic gate using hexa instruction code system. And the 2 auxiliary blocks generate baud rate clock (153.6 KHz, 76.8KHz) to communicate between PLC and computer or programmers.