• Molecules and Cells
• /
• 제28권2호
• /
• pp.75-80
• /
• 2009

The cyclic environmental conditions brought about by the 24 h rotation of the earth have allowed the evolution of endogenous circadian clocks that control the temporal alignment of behaviour and physiology, including the uptake and processing of nutrients. Both metabolic and circadian regulatory systems are built upon a complex feedback network connecting centres of the central nervous system and different peripheral tissues. Emerging evidence suggests that circadian clock function is closely linked to metabolic homeostasis and that rhythm disruption can contribute to the development of metabolic disease. At the same time, metabolic processes feed back into the circadian clock, affecting clock gene expression and timing of behaviour. In this review, we summarize the experimental evidence for this bimodal interaction, with a focus on the molecular mechanisms mediating this exchange, and outline the implications for clock-based and metabolic diseases.

• Journal of Positioning, Navigation, and Timing
• /
• 제8권4호
• /
• pp.209-214
• /
• 2019

Precise point positioning (PPP) requires precise orbit and clock products. International GNSS service (IGS) real-time service (RTS) data can be used in real-time for PPP, but it may not be possible to receive these corrections for a short time due to internet or hardware failure. In addition, the time required for IGS to combine RTS data from each analysis center results in a delay of about 30 seconds for the RTS data. Short-term orbit prediction can be possible because it includes the rate of correction, but the clock correction only provides bias. Thus, a short-term prediction model is needed to preidict RTS clock corrections. In this paper, we used a long short-term memory (LSTM) network to predict RTS clock correction for three minutes. The prediction accuracy of the LSTM was compared with that of the polynomial model. After applying the predicted clock corrections to the broadcast ephemeris, we performed PPP and analyzed the positioning accuracy. The LSTM network predicted the clock correction within 2 cm error, and the PPP accuracy is almost the same as received RTS data.

• ETRI Journal
• /
• 제32권6호
• /
• pp.854-862
• /
• 2010

One-way delay variation (OWDV) has become increasingly of interest to researchers as a way to evaluate network state and service quality, especially for real-time and streaming services such as voice-over-Internet-protocol (VoIP) and video. Many schemes for OWDV measurement require clock synchronization through the global-positioning system (GPS) or network time protocol. In clock-synchronized approaches, the accuracy of OWDV measurement depends on the accuracy of the clock synchronization. GPS provides highly accurate clock synchronization. However, the deployment of GPS on legacy network equipment might be slow and costly. This paper proposes a method for measuring OWDV that dispenses with clock synchronization. The clock synchronization problem is mainly caused by clock skew. The proposed approach is based on the measurement of inter-packet delay and accumulated OWDV. This paper shows the performance of the proposed scheme via simulations and through experiments in a VoIP network. The presented simulation and measurement results indicate that clock skew can be efficiently measured and removed and that OWDV can be measured without requiring clock synchronization.

• 한국정보통신학회논문지
• /
• 제21권5호
• /
• pp.893-898
• /
• 2017

카운터 타입의 시간-디지털 변환기를 공급전압 1.5volts에서 $0.18{\mu}mCMOS$ 공정을 이용하여 설계하였다. 일반적인 시간-디지털 변환기에서는 클록의 주기가 $T_{CK}$일 때, 시작신호와 클록의 시간차에 의해 최대 $T_{CK}$의 변환 에러가 발생한다. 그리고 멈춤신호와 클록의 시간차로 인해 -$T_{CK}$의 에러가 발생한다. 그러나 본 논문에서 제안한 시간-디지털 변환기는 이러한 단점을 보완하기 위해 클록은 시작신호 및 멈춤신호와 동기화하여 회로 내에서 생성되도록 설계하였다. 설계된 시간-디지털 변환기에서 시작신호와 클록의 시간차에 의한 변환에러는 발생하지 않으며, 멈춤신호에 의한 변환에러의 크기는 (1/2)$T_{CK}$로 감소된다.

• 한국측량학회지
• /
• 제25권6_1호
• /
• pp.537-543
• /
• 2007

Since the GPS absolute positioning with pseudorange measurements can significantly be affected by the observation error, the time series analysis of the GPS receiver clock errors was performed in this study. From the estimated receiver clock errors, the time series model is generated, and constrained back in the absolute positioning process. One of the CORS (Continuously Operating Reference Stations) network is used to analyze the behavior of the receiver clock. The dominant part of the model is the linear trend during 24 hours, and the seasonal component is also estimated. After constraining the modeled receiver clock errors, the estimated position error compared to the published coordinates is improved from ${\pm}11.4\;m\;to\;{\pm}9.5\;m$ in 3D RMS.

• 디지털산업정보학회논문지
• /
• 제4권1호
• /
• pp.9-16
• /
• 2008

This paper presents a frequency selection algorithm for minimization power consumption of processor in Mobile System. The proposed algorithm has processor designed low power processor using clock gating method. Clock gating method has improved the power dissipation by control main clock through the bus which is embedded clock block applying the method of clock gating. Proposed method has compared power consumption considered the dynamic power for processor, selected frequency has considered energy gain and energy consumption for designed processor. Or reduced power consumption with decreased processor speed using slack time. This technique has improved the life time of the mobile systems by clock gating method, considered energy and using slack time. As an results, the proposed algorithm reduce average power saving up to 4% comparing to not apply processor in mobile system.

• 한국통신학회논문지
• /
• 제35권12A호
• /
• pp.1128-1135
• /
• 2010

실내 무선 측위를 위한 UWB (Ultra Wide Band) 무선 측위 시스템에서는 정확한 위치 정보를 추정하기 위해 거리 인지 정보를 사용한다. 거리 인지를 위해서는 TOA (Time of Arrival), TDOA (Time Difference of Arrival)와 같은 시간 정보를 기반으로 하는 기법을 사용하는 것이 일반적이며, 시간 정보를 측정하기 위해서는 흔히 클럭 정보를 사용하는데, 이 때 가장 기본적으로 고려해야할 요소가 클럭 동기를 맞추는 것과 클럭 오프셋에 의한 오차를 보상하는 것이다. 본 논문에서는 이를 해결하기 위해 공통 클럭을 이용한 거리 인지 및 무선 측위 기술을 제안한다. 제안하는 무선 측위 기술의 성능 검증을 위하여 IEEE 802.15.4a TG에서 제시한 채널 환경에서 공통 클럭을 이용한 측위 시스템의 거리 인지 및 우선 측위 결과를 확인하기 위한 실험을 진행하였으며, 모의실험 결과를 통하여 클럭 오프셋에 영향을 받지 않는 우선 측위 결과를 얻을 수 있음을 확인하였다.

• 한국통신학회논문지
• /
• 제29권12B호
• /
• pp.1037-1041
• /
• 2004

본 논문에서 위성신호를 매개로 원격지의 로컬클럭이 기준신호에 동기되는 새로운 개념의 슬레이브를럭 시스템을 제안하였으며 이 방식에 의한 실용화 가능성을 확인하였다. 새로이 제시하는 방식은 단계적인 물리계층에 의해 동기되던 기존의 방식에 비해 모든 슬레이브 국소들이 동일한 계위의 품질로 유지될 수 있는 등의 여러 가지 구조적인 장점을 지니고 있다. 슬레이브클럭 시스템의 측정결과 10-12 수준의 주파수정확도를 유지하였으며 ITU-T의 권고(G.811)를 만족하는 MTIE 특성을 보여주었다. 현재 전체적으로 자동화기능을 갖는 초기모델이 구현되었으며 가까운 시일 내에 상용화연구를 통해 통신망 동기용 노드클릭으로 사용될 수 있으리라 기대한다.

• 천문학논총
• /
• 제22권4호
• /
• pp.189-199
• /
• 2007

In this paper, we describe the proposed KVN (Korean VLBI Network) clock system in order to make the observation of the VLBI effectively. In general, the GPS system is widely used for the time information in the single dish observation. In the case of VLBI observation, a very high precise frequency standard is needed to perform the observation in accordance with the observation frequency using the radio telescope with over 100km distance. The objective of the high precise clock system is to insert the time-tagging information to the observed data and to synchronize it with the same clock in overall equipments which used in station. The AHM (Active Hydrogen Maser) and clock system are basically used as a frequency standard equipments at VLBI station. This system is also adopted in KVN. The proposed KVN clock system at each station consists of the AHM, GPS time comparator, standard clock system, time distributor, and frequency standard distributor. The basic experiments were performed to check the AHM system specification and to verify the effectiveness of implemented KVN clock system. In this paper, we briefly introduce the KVN clock system configuration and experimental results.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
• /
• pp.391-393
• /
• 2004

For performance and stability of a synchronized system, we need an efficient Clock Tree Synthesis(CTS) methodology to design clock distribution networks. In a system-on-a-chip(SOC) design environment, CTS effectively distributes clock signals from clock sources to synchronized points on layout design. In this paper, we suggest the pre-layout analysis of the clock network including gated clock, multiple clock, and test mode CTS optimization. This analysis can help to avoid design failure with potential CTS problems from logic designers and supply layout constraints so as to get an optimal clock distribution network. Our new design flow including pre-layout CTS analysis and structural violation checking also contributes to reduce design time significantly.