• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.5
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• pp.1-9
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• 1981

Experimental results on a 4-bit charge-coupled A/D converter are described. Major operations in the successive approximation algorithm are implemented in a monolithic chip, CCADC, which was fabricated usir p-channel CCD technology, with its die size of 4,200 mil2 Typical operating frequency range has been found out to be from 500Hz to 200kHz. In that frequency range, no missing code has been found in the whole signal range of 2.4 volts for ramp signal slewing at 1 LSB/(sampling time). A discussion is made on several layout techniques to conserve the nominal binary ratio of (8:4:2:1) among the areas of four adjacent potential wells (M wells), whose charge storing capacities correspond to each bit magnitude - 3.6 pC, 1.8 pC, 0.9 pC, and 0.45 pC nominal in the order of MSB to the LSB. The effect of 'dump slot', which is responsible for the excessive nonlinearity (2$\frac{1}{2}$LSB) in the A/D converter, is explained. A novel input scheme called 'slot zero insertion' to circumvent the deleterious effects of the dump slot is described with the experimental results.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.6
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• pp.279-283
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• 2012

In is paper, we design and implement the low power, high speed touch screen controller that calculates and outputs the coordinate of touch point on the touch screen of mobile devices. The system clock is 10HMz, the number of input channels is 21, standby current is $20{\mu}A$, dynamic range of input is 140pF~400pF and the response time is 0.1ms/frame. It contains the power management unit for low power, automatic impedance calibration unit in order to adapt to humidity, temperature and evaluation board, adjacent key and pattern interference suppression unit, serial interface unit of I2C and SPI. The function and performance is verified by using FPGA and $0.18{\mu}m$ CMOS standard process. The implemented touch screen is designed for using in the double layer ITO(Indium Thin Oxide) module with diamond pattern and single layer ITO module for cost-effective which are applied to mobile phone or smart remote controller.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.104-111
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• 2002

In this paper, we proposed the architecture of the decoder which implements the multi-view images decoding algorithm. The study of the hardware structure of the multi-view image processing has not been accomplished. The proposed multi-view images decoder operates in a three stage pipelined manner and extracts the depth of the pixels of the decoded image every clock. The multi-view images decoder consists of three modules, Node selector which transfers the value of the nodes repeatedly and Depth Extractor which extracts the depth of each pixel from the four values of the nodes and Affine transformer which generates the projecting position on the image plane from the values of the pixels and the specified viewpoint. The proposed architecture is designed and simulated by the Max+plus II design tool and the operating frequency is 30MHz. The image can be constructed in a real time by the decoder with the proposed architecture.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.7-16
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• 2000

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It performed the division and square-toot by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.148-158
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• 2012

This paper presents the design of the incremental delta-sigma ADC. The proposed circuit consists of pre-amplifier, S & H circuit, MUX, delta-sigma modulator, and decimation filter. Third-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a $0.18{\mu}m$ CMOS technology. The designed circuit show that the modulator achieves 87.8 dB signal-to-noise and distortion ratio (SNDR) over a 5 kHz signal bandwidth and differential nonlinearity (DNL) of ${\pm}0.25$ LSB, integral nonlinearity (INL) of ${\pm}0.2$ LSB. Power consumption of delta-sigma modulator is $941.6{\mu}W$. It was decided that N cycles are 200 clock for 16-bits output.

• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.293-304
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• 2011

In this paper, we proposed a new hardware architecture for motion estimation (ME) which is the most time-consuming unit among H.264 algorithms and designed to the type of intellectual property (IP). The proposed ME hardware consists of buffer, processing unit (PU) array, SAD (sum of absolute difference) selector, and motion vector (MVgenerator). PU array is composed of 16 PUs and each PU consists of 16 processing elements (PUs). The main characteristics of the proposed hardware are that current and reference frames are re-used to reduce the number of access to the external memory and that there is no clock loss during SAD operation. The implemented ME hardware occupies 3% hardware resources of StatixIII EP3SE80F1152C2 which is a FPGA of Altera Inc. and can operate at up to 446.43MHz. Therefore it can process up to 50 frames of 1080p in a second.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.635-637
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• 2013

This paper proposed a new hardware architecture for stereo matching in real time. We minimized the amount of calculation and the number of memory accesses through analyzing calculation of stereo matching. From this, we proposed a new stereo matching calculating cell and a new hardware architecture by expanding it in parallel, which concurrently calculates cost function for all pixels in a search range. After expanding it, we proposed a new hardware architecture to calculate cost function for 2-dimensional region. The implemented hardware can be operated with minimum 250Mhz clock frequence in FPGA environment, and has the performance of 813fps in case of the search range of 64 pixels and the image size of $640{\times}480$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1C
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• pp.112-121
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• 2002

In this paper, we present a design of a hash processor for data security systems. Two standard hash algorithms, Sha-1(American) and HAS-1600(Korean), are implemented on a single hash engine to support real time processing of the algorithms. The hash processor can also be used as a PRNG(Pseudo-random number generator) by utilizing SHA-1 hash iterations, which is being used in the Intel software library. Because both SHA-1 and HAS-160 have the same step operation, we could reduce hardware complexity by sharing the computation unit. Due to precomputation of message variables and two-stage pipelined structure, the critical path of the processor was shortened and overall performance was increased. We estimate performance of the hash processor about 624 Mbps for SHA-1 and HAS-160, and 195 Mbps for pseudo-random number generation, both at 100 MHz clock, based on Samsung 0.5um CMOS standard cell library. To our knowledge, this gives the best performance for processing the hash algorithms.

• Transactions of the Society of Information Storage Systems
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• v.1 no.1
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• pp.34-41
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• 2005

We report some recent results in the rewritable Blu-ray Disc with enhanced overwrite cyclability by using the growth dominant eutectic based Ge(Sb70Te30)+Sb recording layer, GeN interface layer and write strategy optimization. We have developed phase-change optical media with appropriate write strategy for 36(i.e., 1X)-72Mbps(i.e., 2X) dual speed Blu-ray Disc system and fur the future high speed optical data storage. For recording layer, eutectic-based Ge(Sb70Te30)+Sb material was used and Sb/Te ratio and Ge content were optimized to obtain proper erasability and archival stability of recorded amorphous marks. The recording layer is wrapped up in GeN interface layers to obtain overwrite cyclability and higher crystallization speed. In addition, we designed appropriate write strategy so called Time-Shifted Multipulse (TSMP) write strategy where starting position of multipulse parts are shined from reference clock. With this write strategy, the jitter characteristics of the disc was improved and we found that leading edge jitter was improved much more than trailing edge jitter in 1X-2X speed recording. Finally, we investigated the higher speed feasibility of 144Mbps(i.e., 4X) by adopting some elemental doping to the eutectic based Ag-In-Sb-Te recording layer and structural optimization of constitution layers in Blu-ray Disc. In the paper, we report the effect of Sn addition for the feasibility of higher speed recording. The addition of Sn shows increases of the crystallization speed of phase change recording layer.

• Journal of the Society of Disaster Information
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• v.10 no.3
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• pp.374-387
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• 2014

Since the sexual violence crime has a high probability of repeated crime, the electronic monitoring system has been introduced as a measure to it. And this system allows the police to know the location of former criminal around the clock through the electronic device, the former criminal has the psychological/mental oppression which can restrain the intention of crime to a degree. However, there is a limit in blocking criminals with strong will from repeated crime. The next-generation intelligent electronic anklet currently under study collects and analyzes the change bio-data in real time through the location information of electronic monitoring target and attached sensor. This study is aimed to predict the symptom of crime occurrence in advance based on this and block the crime intention in advance or stop the ongoing crime before it is expanded.