• Journal of Advanced Navigation Technology
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• v.24 no.6
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• pp.533-539
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• 2020

Real-time service (RTS) provided by IGS provides correction for GNSS orbit and clock via internet, so it is widely used in fields that require real-time precise positioning. However, the RTS signal may be lost due to an unstable Internet environment. When signal disconnection occurs, signal prediction can be performed using polynomial models. However, the RTS changes rapidly after the GNSS navigation message issue of data (IOD) changes, so it is difficult to predict when signal loss occurs at that point. In this study, we proposed an algorithm to generate continuous RTS correction information by applying the difference in navigation trajectory according to IOD change. The use of this algorithm can improve the accuracy of RTS prediction at IOD changes. After performing optimization studies to improve RTS prediction performance, the predicted RTS trajectory information was applied to precision positioning (PPP). Compared to the conventional method, the position error is significantly reduced, and the error increase along with the signal loss interval increase is reduced.

• Journal of IKEEE
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• v.26 no.4
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• pp.659-670
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• 2022

An 830-Mb/s/pin transceiver for a controller supporting ×32 LPDDR2 memory is designed. The transmitter consists of eight unit circuits has an impedance in the range of 34Ω ∽ 240Ω, and its impedance is controlled by an impedance correction circuit. The transmitted DQS signal has a phase shifted by 90° compared to the DQ signals. In the receive operation, the read time calibration is performed by per-pin skew calibration and clock-domain crossing within a byte. The implemented transceiver for the LPDDR2 memory controller is designed by using a 55-nm process using a 1.2V supply voltage and has a maximum signal transmission rate of 830 Mb/s/pin. The area and power consumption of each lane are 0.664 mm² and 22.3 mW, respectively.

• KEPCO Journal on Electric Power and Energy
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• v.8 no.2
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• pp.159-179
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• 2022

Often a network becomes complex, and multiple entities would get in charge of managing part of the whole network. An example is a utility grid. While the entire grid would go under a single utility company's responsibility, the network is often split into multiple subsections. Subsequently, each subsection would be given as the responsibility area to the corresponding sub-organization in the utility company. The issue of how to make subsystems of adequate size and minimum number of interconnections between subsystems becomes more critical, especially in real-time simulations. Because the computation capability limit of a single computation unit, regardless of whether it is a high-speed conventional CPU core or an FPGA computational engine, it comes with a maximum limit that can be completed within a given amount of execution time. The issue becomes worsened in real time simulation, in which the computation needs to be in precise synchronization with the real-world clock. When the subject of the computation allows for a longer execution time, i.e., a larger time step size, a larger portion of the network can be put on a computation unit. This translates into a larger margin of the difference between the worst and the best. In other words, even though the worst (or the largest) computational burden is orders of magnitude larger than the best (or the smallest) computational burden, all the necessary computation can still be completed within the given amount of time. However, the requirement of real-time makes the margin much smaller. In other words, the difference between the worst and the best should be as small as possible in order to ensure the even distribution of the computational load. Besides, data exchange/communication is essential in parallel computation, affecting the overall performance. However, the exchange of data takes time. Therefore, the corresponding consideration needs to be with the computational load distribution among multiple calculation units. If it turns out in a satisfactory way, such distribution will raise the possibility of completing the necessary computation in a given amount of time, which might come down in the level of microsecond order. This paper presents an effective way to split a given electrical network, according to multiple criteria, for the purpose of distributing the entire computational load into a set of even (or close to even) sized computational loads. Based on the proposed system splitting method, heavy computation burdens of large-scale electrical networks can be distributed to multiple calculation units, such as an RTDS real time simulator, achieving either more efficient usage of the calculation units, a reduction of the necessary size of the simulation time step, or both.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1956-1969
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• 1993

The tilted Huffman trees are used in JPEG and MPEG image compression standards for Huffman coding. In this paper we propose a new decoding technique for Huffman code, symbols are decoded by repeatedly obtaining the predefined number of consecutive bits and accessing symbol tables based on the obtaining bits. We show that the size of the symbol table can be small if the Huffman tree is tilted. Specifically, we show an upper bound on the size in this paper. Since the proposed method processes multiple bits at each clock, it can be used for real time processing. We show such evaluation results.

• Journal of Korean Society of Water and Wastewater
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• v.23 no.6
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• pp.799-810
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• 2009

With time, the stable management of turbidity is becoming more important in the water treatment process. So optimization of coagulation is important for the improvement of the sedimentation efficiency. we evaluated the mixing and hydrodynamic behavior in the coagulation basin using Computational Fluid Dynamics (CFD). The items for evaluation are a location and the speed of agitator and angle of an injection pipe. The results of the CFD simulation, the efficacy of mixing in the coagulation basin was not affected according to one or two injection pipe and angle of an injection pipe. If there is a agitator near outlet of coagulation basin, the efficacy of mixing don't improve even though the speed of agitator increase. So location of agitator is perfect when it locate center at the inlet stream. The coagulation basin at this study, the proper speed of agitator is form 20rpm to 30rpm.

• Journal of Positioning, Navigation, and Timing
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• v.2 no.1
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• pp.33-40
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• 2013

In this paper, GPS signal anomaly generation software is proposed which can be used for the analysis of GPS signal anomaly effect and the design, verification, and operation test of anomalous signal monitoring technique. For the implementation of anomalous signal generation technique, anomalous signals are generated using a commercial signal generation simulator, and their effects and characteristics are analyzed. An error model equation is proposed from the result of analysis, and the anomalous signal generation software is constructed based on this equation. The proposed anomalous signal generation software has high scalability so that users can easily utilize and apply, and is economical as the additional cost for purchasing equipment is not necessary. Also, it is capable of anomalous signal generation based on real-time signal by comparing with the commercial signal generation simulator.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.831-833
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• 2004

In this paper, an obstacle avoidance algorithm is proposed for a network-based robot considering network delay by distribution. The proposed algorithm is based on the VFH(Vector Field Histogram) algorithm, and for the network-based robot system, in which it is assumed robot localization information is transmitted through network communication. In this paper, target vector for the VFH algorithm is estimated through the robot localization information and the measurement of its delay by distribution. The delay measurement is performed by time-stamp method. To synchronize all local clocks of the nodes distributed on the network, a global clock synchronization method is adopted. With the delay measurement, the robot localization estimation is performed by calculating the kinematics of the robot. The validation of the proposed algorithm is performed through the performance comparison of the obstacle avoidance between the proposed algorithm and the existing VFH algorithm on the network-based autonomous mobile robot.

• Journal of Game and Entertainment
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• v.1 no.1
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• pp.31-38
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• 2005

Correct flow of various game manufacture among the justice which is used at the game development. and The understanding about the manufacture regards we making rather correct game. We justice understanding which we are correct in the image manufacture to become the reason air control of the game and We put the center in a 3B game image manufacture understanding. we are marked in maneuvered the game in actual game good. The image of the back of Cut Scene which is inserted at an opeuning incomparableness event time, we have been produced in this method. The thing which a 3D game image is utilized in a special effectiveness image though it is different from the game in the theater movie, we are the graphic which a game manufacture o'clock must be considered. The reason air control which the game player Is rather correct, we are regarded we offer the reason to immerse with his game.

• Journal of the Korea Society of Computer and Information
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• v.4 no.1
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• pp.28-37
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• 1999

In this paper. we developed a delay test architecture and test procedure for clocked 5-bit asynchronous counter circuit based on boundary scan architecture. To develope, we analyze the problems of conventional method on delay test for clocked sequential circuit in boundary scan architecture. This paper discusses several problems of delay test on boundary scan architecture for clocked sequential circuit. Conventional test method has some problems of improper capture timing, of same pattern insertion, of increase of test time. We suggest a delay test architecture and test procedure, is based on a clock count-generation technique to generate continuous clocks for clocked input of CUT. The simulation results or 5-bit counter shows the accurate operation and effectiveness of the proposed delay test architecture and procedure.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.55 no.1
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• pp.26-30
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• 2006

For the purpose of developing capacitive humidity sensor having interdigital electrodes, interdigital electrode was modeled and simulated to obtain capacitance and sensitivity as a function of geometric parameters like the structural gap and thickness. For the development of ASIC, switched capacitor signal processing circuits for capacitive humidity sensor were designed and simulated by Cadence using $0.25{\mu}m$ CMOS process parameters. The signal processing circuits are composed of amplifier for voltage gain control, and clock generator for sensor driving and switch control. The characteristics of the fabricated sensors are; 1) sensitivity is 9fF/%R.H., 2) temperature coefficient of offset(TCO) is $0.4%R.H./^{\circ}C$, 3) nonlinearity is 1.2%FS, 4) hysteresis is 1.5%FS in humidity range of $3%R.H.{\sim}98%R.H.$. The response time is 50 seconds in adsorption and 70 seconds in desorption. Fabricated process used in this capacitive humidity sensor having interdigital electrode are just as similar as conventional IC process technology. Therefore this can be easily mass produced with low cost, simple circuit and utilized in many applications for both industrial and environmental measurement and control system, such as monitoring system of environment, automobile, displayer, IC process room, and laboratory etc.