• Electronics and Telecommunications Trends
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• v.35 no.2
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• pp.69-78
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• 2020

Small portable devices such as mobile phones and laptops currently display a trend of high power consumption owing to their characteristics of high speed and multifunctionality. Low-power SoC design is one of the important factors that must be considered to increase portable time at limited battery capacities. Popular low power SoC design techniques include clock gating, multi-threshold voltage, power gating, and multi-voltage design. With a decreasing semiconductor process technology size, leakage power can surpass dynamic power in total power consumption; therefore, appropriate low-power SoC design techniques must be combined to reduce power consumption to meet the power specifications. This study examines several low-power SoC design trends that reduce semiconductor SoC dynamic and static power using EDA tools. Low-power SoC design technology can be a competitive advantage, especially in the IoT and AI edge environments, where power usage is typically limited.

• Proceedings of the IEEK Conference
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• summer
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• pp.61-65
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• 2004

An on-chip debugging unit is proposed aiming performance enhancement of JTAG-based SoC systems. The proposed unit comprises a JTAG module and a core breaker. The IEEE 1149.1 standard has been modified and applied to the new JTAG module. The proposed unit eliminates redundant clock cycles included in the TAP command execution stage reducing overall debugging time. TAP execution commands are repeatedly issued to perform debugging of complicated SoC systems. Simulation on the proposed unit shows some $14\%$ performance enhancement and $50\%$ gate count reduction compared to the conventional ones.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.78-83
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• 1996

A timing recovery circuit of 10 Gbit/s optical receiver is described. The circuit consists of a passive NRZ-to-PRZ circuit, a dielectric resonator filter (DRF) and a narrow band amplifier, which for the first time adopted a temperature compensation technique using the tempareature characteristics of DR. The experimental results showed an output clock phase variation of less than ${\pm}$6 degree over the operating temperature range form 0$^{\circ}C$ to 75$^{\circ}C$ and measured maximum rms jitters of less than 2 phs with the resonance detunings of up to ${\pm}$10 MHz. These experimental results show that the circuit is a suitable for 10 Gbit/s lightwave transmission system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.344-350
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• 2011

Higher integrated density in 3D ICs also brings the difficulties of routing, which can cause the routing failure or re-design from beginning. Hence, precise congestion estimation at the early physical design stage such as floorplan is beneficial to reduce the total design time cost. In this paper, an effective estimation method of routing congestion is proposed for 3D ICs at floorplan stage. This method uses synthesized virtual signal nets, power/ground network and clock network to achieve the estimation. During the synthesis, the TSV location is also under consideration. The experiments indicate that our proposed method had small difference with the estimation result got at the post-placement stage. Furthermore, the comparison of congestion maps obtained with our method and global router demonstrates that our estimation method is able to predict the congestion hot spots accurately.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.4
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• pp.293-300
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• 2009

In this paper, we describe a method for synchronization protocol method used in control system based on network and IEEE 1599 synchronization method which used for implementation of synchronization technology of advanced industrial Ethernet. We also implement and perform the experiment for synchronization technology of EtherCAT communication which is one of the industrial Ethernet technology used IEEE 1599 synchronization technology based on time. And we describe an evaluation for experiment result, improve the problem and future plan.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.4
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• pp.644-650
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• 2001

A remotely located synchronization system which is locked to the remote master clock has been implemented by using GPS Common-View technique. The measurement results showed that the accuracy of the remote synchronization system could be kept within a few parts in $10^{-12}$ and MTIE(Maximum Time Interval Error) met the ITU-T Recommendation(G.811). A prototype system having fully automatic operational functions has been realized up to now and is expected to be used in the network synchronization in the near future.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.11
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• pp.17-26
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• 1993

In this paper, a VlSI architecture for Reed-Solomon (RS) decoder based on the Berlekamp algorithm is proposed. The proposed decoder provided both erasure and error correcting capability. In order to reduc the chip area, we reformulate the Berlekamp algorithm. The proposed algorithm possesses a recursive structure so that the number of cells for computing the errata locator polynomial can be reduced. Moreover, in our approach, only one finite field multiplication per clock cycle is required for implementation, provided an improvement in the decoding speed, and the overall architecture features parallel and pipelined structure, making a real time decoding possible. From the performance evaluation, it is concluded that the proposed VLSI architecture is more efficient in terms of VLSI implementation than the rcursive architecture based on the Euclid algorithm.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2476-2479
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• 1998

The masticatory muscle relaxation appliance is developed to improve the malhabit of tooth clenching of the wearer. The repeated clenching of the tooth causes excessive attrition of tooth set. The intraoral appliance measures the tooth clenching pressure data and transmits the data to masticatory muscle relaxation appliance. The appliance compares the pressure data with the reference value and generates the warning signal. The relaxation appliance also stores the clenching pressure data for clenching habit analysis. The appliance is designed with a microprocessor, real time clock, nonvolatile read write memory and dual serial communication ports.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.9 no.1
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• pp.30-38
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• 1984

In this paper, we designed the programmable 2nd order switched capacitor filter that the center frequency can be varied linearly with the clock frequency, and that the peak gaion and the selectivity can be controlled with digital signal by the capacitor array. In addition, speech synthesizer system was constructed with this filter, korean consonants being synthesized. Therefore, this filter shows the possibility that most Korean language sounds can be synthesized in the real time mode.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.3
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• pp.68-68
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• 2001

본 논문에서는 3GPP와 ETSI에서 IMT-2000의 음성부호화 방식 표준안으로 채택한 AMR 음성부호화 알고리즘을 분석하고 C 컴파일러와 어셈블리 언어를 이용한 최적화 과정을 거친 후, 고정 소수점 DSP 칩인 TMS320C6201을 이용하여 실시간 구현하였다. 구현된 codec의 프로그램 메모리는 약 31.06 kWords, 데이터 RAM 메모리는 약 9.75 kWords, 그리고 데이터 ROM 메모리는 약 19.89 kWords 정도를 가지며, 한 프레임(20 ms)을 처리하는데 약 4.38 ms가 소요되어 TMS320C6201 DSP 칩의 전체 가용한 clock의 21.94%만 사용하여도 충분히 실시간으로 동작 가능함을 확인하였다. 또한, DSP 보드상에서 구현한 결과가 ETSI에서 공개한 ANSI C 소스 프로그램의 수행 결과와 일치함을 검증하였고, 구현된 AMR 음성부호화기를 sound I/O 모듈과 결합하여 실험한 결과, 어떠한 음질의 왜곡이나 지연 없이 실시간으로 충분히 동작함을 확인하였다. 마지막으로, Host I/O와 LAN 케이블을 이용하여 AMR 음성부호화 알고리즘을 통한 쌍방간 실시간 통신을 full-duplex 모드로 확인하였다.