• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.1
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• pp.1-8
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• 1999

In order to provide appropriate Quality of Service(QoS) guarantee to each traffic flow in intergrated service networks, an efficient traffic scheduling algorithm as well as resource reservation must be adopted in host and transit routers. In this paper, a new efficient fair queueing algorithm which adopts a linearly increasing virtual time is presented. The proposed algorithm is fair and the maximum and mean delay guaranteed of each flow are less than those of the SCFQ(self clocked fair queueing) algorithm which is one of the most promising traffic scheduling algorithm, while providing low implementation complexity as the SCFQ scheme. And, it has the better isolation provided than SCFQ, which means that each flow is much less influenced by the violating traffic flows provided its allocated bandwidth gurantee. The fairness of the proposed algorithm is proved and simulation results of maximum and mean delay presented.

• Journal of IKEEE
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• v.24 no.1
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• pp.52-58
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• 2020

This paper describes a hardware implementation of a true random number generator (TRNG) for information security applications. A new approach for TRNG design was proposed by adopting random transition rules in cellular automata and applying different transition rules at every time step. The TRNG circuit was implemented on Spartan-6 FPGA device, and its hardware operation generating random data with 100 MHz clock frequency was verified. For the random data of 2×10⁷ bits extracted from the TRNG circuit implemented in FPGA device, the randomness characteristics of the generated random data was evaluated by the NIST SP 800-22 test suite, and all of the fifteen test items were found to meet the criteria. The TRNG in this paper was implemented with 139 slices of Spartan-6 FPGA device, and it offers 600 Mbps of the true random number generation with 100 MHz clock frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.1002-1005
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• 2015

Mobile operating systems have been typically classified into Apple and Android. Samsung showed its own new mobile OS developing Tizen based on Linux kernel. Mobile operating system has developed a technology using low-power by itself because of the limitation of capacity of battery, a feature of mobile. Samsung Tizen OS has a low-power technology called Power Manager controling LCD states as users'inputs or time-out events occur. However, if users'input occurs frequently, energy consumption jumped before-and-after users'input because CPU clock is increased rapidly due to overhead increase for frequent LCD state changes. This paper proposes a mechanism to reduce the overhead for LCD state changes, when user's input is frequent, by adding a new state to the Power Manager the current Tizen OS is using. We have implemented the proposed mechanism at Tizen phone kernel layer in this paper and experimented the mechanism according to users' LCD touch inputs. The experiment shows that it is possible to decrease energy by reducing the CPU clock increase according to the frequent user's inputs.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.453-464
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• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

• The KIPS Transactions:PartC
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• v.16C no.2
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• pp.229-236
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• 2009

UWB signal with high resolution capability can be used to estimate ranging and positioning in wireless personal area networks. The clock frequency differences of nodes have serious affects on asynchronous ranging methods to estimate locations of mobile nodes. The specification of high rate UWB describes successive TWR method with the estimation of a relative clock frequency offset. In this paper, we complete the ranging equations using relative frequency offset and time information, and propose a method to estimate the exact frequency offsets. We evaluate the ranging algorithms with simulation. The results show that the performances of the algorithms using frequency offsets are very close without noise. But, at noise environment, the method of exact frequency offsets shows better performance than that of relative frequency offsets.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.255-260
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• 2001

This paper describes the design of the Register Controlled DLL(Delay-Locked Loop) that achieves fast locking and low Power consumption using a new locking algorithm. A fashion for a fast locking speed is that controls the two controller in sequence. The up/down signal due to clock skew between a internal and a external clock in phase detector, first adjusts a large phase difference in coarse controller and then adjusts a small phase difference in fine controller. A way for a low power consumption is that only operates one controller at once. Moreover the proposed DLL shows better jitter performance Because using the lock indicator circuit. The proposed DLL circuit is operated from 50MHz to 200MHz by SPICE simulation. The estimated power dissipation is 15mA at 200MHz in 3.3V operation. The locking time is within 7 cycle at all of operating frequency.

• Structural Engineering and Mechanics
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• v.73 no.4
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• pp.427-436
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• 2020

The use of final IGS precise orbit and clock products for high-rate GNSS-PPP proved its effectiveness in capturing dynamic displacement of engineering structures caused by earthquakes. However, the main drawback of using the final products is that they are available after approximately two weeks of data collection, which is not suitable for timely measures after an event. In this study, the use of ultra-rapid products (observed part), which are available after a few hours of data collection, and rapid products, which are available in less than 24 hrs, are investigated and their results are compared to the more precise final products. The tests are designed such that harmonic oscillations with different frequencies and amplitudes and ground motion of a simulated real earthquake are generated using a single axis shake table and the PPP was used to capture these movements by monitoring time-change of the table positions. To evaluate the accuracy of PPP using ultra-rapid, rapid and final products, their results were compared with relative GNSS positioning and LVDT (Linear Variable Differential Transformer) data, treated as reference. The results show that the high-rate GNSS-PPP solutions based on the three products can capture frequencies of harmonic oscillations and dynamic displacement with good accuracy. There were slight differences between ultra-rapid, rapid and final products, where some of the tested events indicated that the latter two produced are more accurate and provide better results compared to the ultra-rapid product for monitoring short-term dynamic displacements.

• Journal of Korean Academy of Nursing
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• v.51 no.3
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• pp.294-304
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• 2021

Purpose: This study aimed to investigate objectively measured physical activity (PA) in institutionalized older adults with mild cognitive impairment (MCI) and to elucidate the influence of autonomic nervous function, salivary cortisol, and PA on cognitive functions based on neurovisceral integration model. Methods: Overall cognitive function was evaluated using the mini-mental state examination (MMSE) and executive function was evaluated using semantic verbal fluency test and clock drawing test. Actigraph for PA, HRV and sAA for autonomous function, and the geriatric depression scale for depression were used. Saliva specimens were collected in the morning for sAA and cortisol. Results: Ninety-eight older adults from four regional geriatric hospitals participated in the study. They took 4,499 steps per day on average. They spent 753.93 minutes and 23.12 minutes on average in sedentary and moderate-to-vigorous activity, respectively. In the multiple regression analysis, lower salivary cortisol level (β = - .33, p = .041) and greater step counts (β = .37, p = .029) significantly improved MMSE score. Greater step count (β = .27, p = .016) also exerted a significant influence on verbal fluency, and greater sAA (β= .35, p = .026) was significantly associated with a better clock drawing test result. Conclusion: Salivary cortisol, sAA and physical activity were significantly associated with cognitive functions. To prevent older adults from developing dementia, strategies are needed to increase their overall PA amount by decreasing sedentary time and to decrease salivary cortisol for cognitive function, and to maintain their sympathetic nervous activity for executive function.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.3
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• pp.355-366
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• 2022

This paper proposes a microcode-based neural network accelerator controller for artificial intelligence accelerators that can be reconstructed using a programmable architecture and provide the advantages of low-power and ultra-small chip size. In order for the target accelerator to support various neural network models, the neural network model can be converted into microcode through microcode compiler and mounted on accelerator to control the operators of the accelerator such as datapath and memory access. While the proposed controller and accelerator can run various CNN models, in this paper, we tested them using the YOLOv2-Tiny CNN model. Using a system clock of 200 MHz, the Controller and accelerator achieved an inference time of 137.9 ms/image for VOC 2012 dataset to detect object, 99.5ms/image for mask detection dataset to detect wearing mask. When implementing an accelerator equipped with the proposed controller as a silicon chip, the gate count is 618,388, which corresponds to 65.5% reduction in chip area compared with an accelerator employing a CPU-based controller (RISC-V).

• Journal of Marine Life Science
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• v.9 no.1
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• pp.47-52
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• 2024

Light is a major external environmental factor that influences the circadian rhythm of photosynthetic organisms and various physiological phenomena, such as growth, maturation, and behavior. The number of light-reaching organisms changes depending on the season and atmospheric conditions, and the intensity and wavelength of light differ depending on the organisms inhabiting the environment. Altered light changes the circadian rhythm of fish, which is controlled by clock genes, such as period 2 (Per2), cryptochrome 1 (Cry1), and melatonin. In this study, we set the zeitgeber time (ZT; 14 light-10 dark, LD) based on the actual sunrise and sunset times and examined Per2 and Cry1 activities, levels of aralkylamine N-acetyltransferase (AANAT), and melatonin in Pholis nebulosa, a drifting seaweed species exposed to irregular light. Per2 and Cry1 levels increased during the daytime and decreased after sunset. The AANAT levels decreased during the daytime and increased during the night. Melatonin concentration was highest around midnight (ZT21, 23:30), but exhibited similar concentrations during the daytime. While the activity of Per2, Cry1, and AANAT levels exhibited a typical circadian rhythm observed in most vertebrates, melatonin concentrations did not show a significant difference between the daytime and nighttime. These findings provide insights into the circadian rhythm patterns of organisms exposed to irregular light environments, such as P. nebulosa, which differ from those of typical fish species.