• 유체기계공업학회:학술대회논문집
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• 2006.08a
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• pp.383-386
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• 2006

In this study, we propose a new fast algorithm for calculating short range forces in molecular dynamics, This algorithm uses a new hierarchical tree data structure which has a high adaptiveness to the particle distribution. It can divide a parent cell into k daughter cells and the tree structure is independent of the coordinate system and particle distribution. We investigated the characteristics and the performance of the tree structure according to k. For parallel computation, we used orthogonal recursive bisection method for domain decomposition to distribute particles to each processor, and the numerical experiments were performed on a 32-node Linux cluster. We compared the performance of the oct-tree and developed new algorithm according to the particle distributions, problem sizes and the number of processors. The comparison was performed sing tree-independent method and the results are independent of computing platform, parallelization, or programming language. It was found that the new algorithm can reduce computing cost for a large problem which has a short search range compared to the computational domain. But there are only small differences in wall-clock time because the proposed algorithm requires much time to construct tree structure than the oct-tree and he performance gain is small compared to the time for single time step calculation.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.5
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• pp.225-233
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• 2004

A novel real-time color gamut mapping method is described. The color gamut mapping method that is used for enhancing the color reproduction quality between PC monitor and printer devices is adopted for digital TV display quality enhancement. The high definition digital TV display devices operate at the clock speed of around 70MHz ～ 150MHz and permit several nano seconds for real-time gamut mapping. Thus, the concept of three-dimensional reduced resolution look-up table is introduced for real-time processing. The required hardware can be greatly reduced by look-up table resolution adjustment. The proposed hardware architecture is successfully implemented in FPGA and ASIC and also successfully adopted in digital TV display quality enhancement purposes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.41-50
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• 2005

As the size of circuits becomes larger, the test method needs more test data volume and larger test application time. In order to reduce test data volume and test application time, a new test data compression/decompression method is proposed. The proposed method is based on an XOR network uses don't-care-bits to improve compression ratio during seed vectors generation. After seed vectors are produced seed vectors can be merged using two prefix codes. It only requires 1 clock time for reusing merged seed vectors, so test application time can be reduced tremendously. Experimental results on large ISCAS '89 benchmark circuits prove the efficiency of the proposed method.

• Aerospace Engineering and Technology
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• v.8 no.2
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• pp.92-97
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• 2009

Two conventional speed detection methods (Elapsed-time method and Pulse-count method) are analyzed and compared for a high speed motor with digital tacho pulse with non-uniformity. In general, the elapsed-time method usually has better performance than a pulse-count method in case sufficiently high speed clock is used to measure the time difference. But if a tacho pulse non-uniformity exists in the reaction wheel - most of reaction wheel has a certain amount of non-uniformity - the accuracy of the elapsed-time method is degraded significantly. Thus the performance degradation is analyzed with respect to the level of non-uniformity of tacho pulse distribution and an allowable bound is suggested.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.200-203
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• 2003

By minimizing the burst error of data and correcting the error, we can define the convolution coding and interleaving in IEEE 802.11a wireless tan system. Two step block interleaver was decided by coded bits per OFDM symbol and due to this it comes to the delay time in IEEE 802.11a. This is the point of the question which we must consider. We try to decrease the delay time by all 48-clock from interleavings, and we have proposed a way carried out the interleaving outputs per symbol. So in comparison with the existing interleaver, we can decrease the delay time in reading and writing data, as well as reduce the delay time of bit re-ordering per symbol. Also this scheme is apply in all x-QAM cases.

• Journal of Positioning, Navigation, and Timing
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• v.11 no.4
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• pp.269-277
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• 2022

In this paper, we overview the system development status of the national maritime precise point positioning-real-time kinematic (PPP-RTK) service in Korea, also known as the Precise POsitioning and INTegrity monitoring (POINT) system. The development of the POINT service began in 2020, and the open service is scheduled to start in 2025. The architecture of the POINT system is composed of three provider-side facilities-a reference station, monitoring station, and central control station-and one user-side receiver platform. Here, we propose the detailed functionality of each component considering unidirectional broadcasting of augmentation data. To meet the centimeter-level user positioning accuracy in maritime coverage, new reference stations were installed. Each reference station operates with a dual receiver and dual antenna to reduce the risk of malfunctioning, which can deteriorate the availability of the POINT service. The initial experimental results of a testbed from corrections generated from the testbed network, including newly installed reference stations, are presented. The results show that the horizontal and vertical accuracies satisfy 2.63 cm and 5.77 cm, respectively. For the purpose of (near) real-time broadcasting of POINT correction data, we designed a correction message format including satellite orbit, satellite clock, satellite signal bias, ionospheric delay, tropospheric delay, and coordinate transformation parameters. The (near) real-time experimental setup utilizing (near) real-time processing of testbed network data and the designed message format are proposed for future testing and verification of the system.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.9 no.1
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• pp.115-126
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• 1999

As the processing speed of communication and computer system has been improved, high speed data processing is required to correct error of data. In this paper, decoding algorithm which is applicable to the wireless communication system is proposed and encoder and decoder are designed by using the proposed decoding algorithm. We design the encoder and decoder by using the VHDL(VHSIC Hardware Description Language) and simulate the designed encoder and decoder by using V-system. Designed algorithm is synthesized by using synopsys tools and is made to one chip by means of XILINX XC4010EPC84-4. When 20MHz was used as the input clock, data arrival time was 29.20ns and data require time was 48.70ns.

• Journal of Semiconductor Engineering
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• v.2 no.1
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• pp.109-118
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• 2021

This review paper describes the overall operating principle of a discrete-time delta-sigma modulator (DTDSM) and a continuous-time delta-sigma modulator (CTDSM) using a switched-capacitor (SC). In addition, research that has solved the problems related to each delta-sigma modulator (DSM) is introduced, and the latest developments are explained. This paper describes the chopper-stabilization technique that mitigates flicker noise, which is crucial for the DSM. In the case of DTDSM, this paper addresses the problems that arise when using SC circuits and explains the importance of the operational transconductance amplifier performance of the first integrator of the DSM. In the case of CTDSM, research that has reduced power consumption, and addresses the problems of clock jitter and excess loop delay is described. The recent developments of the analog front end, which have become important due to the increasing use of wireless sensors, is also described. In addition, this paper presents the advantages and disadvantages of the three-opamp instrumentation amplifier (IA), current feedback IA (CFIA), resistive feedback IA, and capacitively coupled IA (CCIA) methods for implementing instrumentation amplifiers in AFEs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1047-1054
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• 2004

In this paper, we present two systolic arrays for computing multiplications in CF(2$\^$m/) generated by an irreducible all one polynomial (AOP). The proposed two systolic mays have parallel-in parallel-out structure. The first systolic multiplier has area complexity of O(㎡) and time complexity of O(1). In other words, the multiplier consists of m(m+1)/2 identical cells and produces multiplication results at a rate of one every 1 clock cycle, after an initial delay of m/2+1 cycles. Compared with the previously proposed related multiplier using AOP, our design has 12 percent reduced hardware complexity and 50 percent reduced computation delay time. The other systolic multiplier, designed for cryptographic applications, has area complexity of O(m) and time complexity of O(m), i.e., it is composed of m+1 identical cells and produces multiplication results at a rate of one every m/2+1 clock cycles. Compared with other linear systolic multipliers, we find that our design has at least 43 percent reduced hardware complexity, 83 percent reduced computation delay time, and has twice higher throughput rate Furthermore, since the proposed two architectures have a high regularity and modularity, they are well suited to VLSI implementations. Therefore, when the proposed architectures are used for GF(2$\^$m/) applications, one can achieve maximum throughput performance with least hardware requirements.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.12
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• pp.1-9
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• 2001

In the APON(ATM Passive Optical Network), the transmission of the upstream traffic is based on a TDMA(Time Division Multiple Access) method that an OLT(Optical Line Termination) permits ONUs(Optical Network Units) sending cells by allocating time slots. Because the upstream is not a streaming mode, the cell synchronizer has to be operated in the burst mode. Also, the cell phase monitor is required to prevent collisions between cells which are transmitted by multiple ONUs through a single optical fiber. In this paper, a TDMA burst cell synchroniser is implemented with the FPGA(Field Programmable Gate Array) being used in the APON based on G.983.1 for transmitting upstream cells. It has two main functions which are the upstream data recovery and the phase monitoring. The former is to recover the upstream data and clock in the OLT by seeking the preamble which is the overhead of the upstream time slot and by aligning the phase of the bit and cell with the system clock. The latter is to provide the information to the ONU to compensate for the equalization delay by monitoring continuously the phase difference between adjacent cells to avoid the cell collision on the upstream.