• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.109-116
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• 2014

This paper presents a high-efficiency digital class-D audio amplifier using a composite interpolation filter for portable audio devices. The proposed audio amplifier is composed of an interpolation filter, a delta-sigma modulator, and a class-D output stage. To reduce power consumption, the designed interpolation filter has an optimized composite structure that uses a direct-form symmetric and Lagrange FIR filters. Compared to the filters with homogeneous structures, the hardware cost and complexity are reduced by about half by the optimization. The coefficients of the digital delta-sigma modulator are also optimized for low power consumption. The class-D output stage has gate driver circuits to reduce shoot-through current. The implemented class-D audio amplifier exhibited a high efficiency of 87.8 % with an output power of 57 mW at a load impedance of $16{\Omega}$ and a power supply voltage of 1.8 V. An outstanding signal-to-noise ratio of 90 dB and a total harmonic distortion plus noise of 0.03 % are achieved for a single-tone input signal with a frequency of 1 kHz.

• 한국정보통신학회논문지
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• 제10권1호
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• pp.49-56
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• 2006

본 논문에서는 송신기의 전력효율을 고려하여 C급 전력증폭기를 사용함으로 인한 증폭기의 비선형성의 영향을 극복하기 위해 일정진폭 특성과 연속위상특성을 갖는 CE-CPSK 변조 직접 대역확산 송수신기를 제안하였다. 직접 대역확산 수신기의 초기동기 성능을 평균 동기 획득시간, 검출확률을 통해 기존의 BPSK 변조방법과 CE-CPSK변조방법에 대해 다중사용자환경하에서의 성능을 비교분석하였다. 비선형성을 지닌 채널 환경 하에서 제안한 CE-CPSK 변조방식이 기존의 BPSK 변조방식에 비해 부대엽 스펙트럼이 상당히 감소되는 것을 알 수 있었으며 코드 동기 획득 성능 또한 우수함을 알 수 있었다.

• Transactions on Electrical and Electronic Materials
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• 제14권5호
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• pp.235-241
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• 2013

A low power CMOS control circuit is applied in an integrated DC-DC buck converter. The integrated converter is composed of a feedback control circuit and power block with 0.35 ${\mu}m$ CMOS process. A current-sensing circuit is integrated with the sense-FET method in the control circuit. In the current-sensing circuit, a current-mirror is used for a voltage follower in order to reduce power consumption with a smaller chip-size. The N-channel MOS acts as a switching device in the current-sensing circuit where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time. The converter offers well-controlled output and accurately sensed inductor current. Simulation work shows that the current-sensing circuit is operated with an accuracy of higher than 90% and the transient time of the error amplifier is controlled within $75{\mu}sec$. The sensing current is in the range of a few hundred ${\mu}A$ at a frequency of 0.6~2 MHz and an input voltage of 3~5 V. The output voltage is obtained as expected with the ripple ratio within 1%.

• 대한전자공학회논문지SD
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• 제39권7호
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• pp.97-103
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• 2002

본 논문은 레이더 시스템이나 위성 통신용으로 사용되어지는 LVA(Logarithmic Video Amplifier) 설계에 관한 내용이다. 제안된 LVA는 입력단, 증폭단, 그리고 출력단으로 나뉘어진다. 넓은 동작 영역과 고속특성을 갖도록 새로운 직 ${\cdot}$ 병렬 구조를 제안하였으며 LVA와 전단인 Detector Diode와의 입력 범위 조절을 위하여 새로운 입력단을 설계하였다. 제안된 LVA는 1.5 um, 2-poly, 2-Metal, n-well, BiCMOS, 공정을 사용하였으며, 유효 칩 면적은 1310 um x 1540 um 고 10V 전압에서 190 mW 의 전력 소모를 나타내었다. 모의 실험 및 측정을 통하여 60 dB의 동작영역과 100 ns의 falling time을 나타내었다.

• 한국전자파학회지:전자파기술
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• 제11권4호
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• pp.39-52
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• 2000

A design of 2 stage S-DLVA(successive detector log video amplifier) was studied to detect wide dynamic radar pulse ranging from -70 ㏈m to 0㏈m. A basic design idea was focused on the linear detection in logarithmic scale of wide dynamic range radar pulses from nosie-like weak power of -70 ㏈m to relatively high power 0 ㏈m. It is highly formidable, since it requires high speed detection less than 10 nsec over the operating frequency ranges from 6 to 18 ㎓. A limiter diode, a tunnel diode and an L17-C were used as a protecting device, a detector diode and a log video amplifier in companion as a single stage detector to give voltage output proportional to the input power of about 35 ㏈ dynamic range. A protype of 2-stage DLVA having one more single stage detector was fabricated with a 32 ㏈ low noise amplifier and a 3 ㏈ hybrid coupler to provide total 70 ㏈ dynamic range detection. The logging characteristics were measured to have log slope of 25m.V/㏈ against 70 ㏈ logging range from -55 ㏈m to +15 ㏈m, the log linearity of within +/- 1.5 ㏈, and tangential sensitivity was at -63 ㏈m. The pulse dynamics of rise time and recovery time were measured as 50 nsec and 1.2 $\mu$sec, respectively. The reason might be due to the parasitic capacitances of packaged limiter, tunnel diode, and L17-C.

• IEIE Transactions on Smart Processing and Computing
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• 제5권1호
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• pp.5-9
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• 2016

The modulation bandwidth of a reflective semiconductor optical amplifier (RSOA) is limited by carrier lifetime. Therefore, it is hard to directly modulate an RSOA with high-speed electrical signals. We theorize that an optical filter can act as an optical equalizer, compensating for the narrow bandwidth limitation imposed by the RSOA. By modeling a time-varying RSOA with a modified transfer matrix method (TMM), we simulated 25 Gbps operation of an RSOA with optical filtering effects. We investigated the impact of detuning the center wavelength of the optical filter on the modulation of an RSOA. The numerical results show that it is possible to modulate an RSOA with an optical filtering effect at 25 Gbps without electronic equalization or digital signal processing.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2001년도 종합학술발표회 논문집 Vol.11 No.1
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• pp.257-261
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• 2001

This paper presents the implementation of wide-band RFIC amplifier operating from near 50MHz to 3GHz using Tachyonics SiGe HBT foundry. Voltage shunt feedback is used for the flat gain and the broad band impedance matching. Initial design parameters are calculated using the low frequency small signal analysis. Since the HBT model was not available at the design time, discrete tuning board was made for fine tuning in the low frequency range. Fabricated amplifier shows 12dB gain with 1dB fluctuation and PldB reaches 15dBm at 850MHz.

• 한국전자파학회논문지
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• 제15권3호
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• pp.251-257
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• 2004

연안에서 선박의 안전한 항행과 관제를 위해 선박간 또는 선박과 관제소간의 항행정보를 교환할 수 있도록 하는 AIS(Automatic Identification System)는 운용 방식(Low setting, High setting)에 따라 서로 다른 송신 출력 크기를 가지며, 1 ms(Transmitter Setting Time)안에 각각의 최종 출력 크기 의 20% 이내로 도달하도록 하는 동작 성능을 요구한다. 본 논문에서는 이와 같은 AIS의 송신 출력 특성에 부합할 수 있도록 전력 증폭기 모듈에 적절한 궤환 회로를 제안하고 이를 설계, 제작하였다.

• Journal of the Optical Society of Korea
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• 제18권5호
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• pp.442-448
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• 2014

For the first time, a novel analytical model of the net gain for a Raman-EDFA hybrid optical amplifier (HOA) is proposed and its various parameters optimized using a genetic algorithm. Our method has been shown to be robust in the simultaneous analysis of multiple parameters (Raman length, EDFA length, and pump powers) to obtain large gain. The optimized HOA is further investigated at the system level for the scenario of a 50-channel DWDM system with 0.2-nm channel spacing. With an optimized HOA, a flat gain of >17 dB is obtained over the effective ITU-T wavelength grid with a variation of less than 1.5 dB, without using any gain-flattening technique. The obtained noise figure is also the lowest value ever reported for a Raman-EDFA HOA at reduced channel spacing.

• 한국자기학회지
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• 제15권6호
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• pp.332-335
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• 2005

자속계의 경우 입력전압을 적분하여야 되기 때문에 연산증폭기의 입력 바이어스 전류가 있으면 적분기의 출력이 드리프트하게 된다. 본 연구에서는 이 드리프트를 자동으로 측정하고 보상하기 위하여 전압변동이 없는 디지털 sample and hold증폭기를 자속계에 도입하여 제작하였다. 개발한 자속계의 경우 적분기의 시간상수 $RC=10^{-3}$ s에서 드리프트가 $5{\times}10^{-8}\;Wb/s$ 이하였다.