• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 1996년도 추계학술대회 논문집
• /
• pp.702-706
• /
• 1996

The King Sejong's Striking water-clock was named for its distictive day and night time announcing system. Its time announcing system generates acoustic and visual signals for the twelve double hour, and combinations of two different acoustic signals for the five night watches, The mechanism of this signal generation system is triggered by a copper ball which is mechanically digitized time keeping signal, and is generated from the water clock. The time announcing system consisted four parts: 1) the mechanical amplifier which changes small copper to heavy steel ball, 2) day time announcing system, 3) night time announcing system, 4) sounding mechanism. The time announcing system of King Seong's Striking Clepsidra is remotely related to the Arabic clock system, however, it does have world-widely distictive mechanisms of its era, such as mechanical amplifier, self-weight rachet mechanism, and resetable mechanical computer etc.

• Journal of Semiconductor Engineering
• /
• 제2권1호
• /
• pp.109-118
• /
• 2021

This review paper describes the overall operating principle of a discrete-time delta-sigma modulator (DTDSM) and a continuous-time delta-sigma modulator (CTDSM) using a switched-capacitor (SC). In addition, research that has solved the problems related to each delta-sigma modulator (DSM) is introduced, and the latest developments are explained. This paper describes the chopper-stabilization technique that mitigates flicker noise, which is crucial for the DSM. In the case of DTDSM, this paper addresses the problems that arise when using SC circuits and explains the importance of the operational transconductance amplifier performance of the first integrator of the DSM. In the case of CTDSM, research that has reduced power consumption, and addresses the problems of clock jitter and excess loop delay is described. The recent developments of the analog front end, which have become important due to the increasing use of wireless sensors, is also described. In addition, this paper presents the advantages and disadvantages of the three-opamp instrumentation amplifier (IA), current feedback IA (CFIA), resistive feedback IA, and capacitively coupled IA (CCIA) methods for implementing instrumentation amplifiers in AFEs.

• Journal of the Optical Society of Korea
• /
• 제17권3호
• /
• pp.237-241
• /
• 2013

This paper presents an efficient evolutionary method to optimize the gain ripple of multi-pumps photonic crystal fiber Raman amplifier using the Fuzzy Adaptive Modified PSO (FAMPSO) algorithm. The original PSO has difficulties in premature convergence, performance and the diversity loss in optimization as well as appropriate tuning of its parameters. The feasibility and effectiveness of the proposed hybrid algorithm is demonstrated and results are compared with the PSO algorithm. It is shown that FAMPSO has a high quality solution, superior convergence characteristics and shorter computation time.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
• /
• pp.581-584
• /
• 2003

The phase differences and noise signals are in general serious on output of a instrumentation amplifier for signal conditioning of a sensor driven at high frequency due to a time-varying input signal. In this study, we get the better amplification and S/N ratio using the rectified signal for the input of instrumentation amplifier. This driving circuits were designed and constructed by OrCAD and laboratory PCB process. All of the elements used on the circuit including highly speedy OP-Amp. was SMD type and the MI sensor was fabricated by meander-patterned amorphous ribbon. The output sensitivity of this circuit was $105.3mV/V{\cdot}Oe$. That's why this driving circuit is good at detection of fine magnetic field.

• 대한의용생체공학회:의공학회지
• /
• 제17권2호
• /
• pp.179-188
• /
• 1996

A clinically oriented 32-channel electroencephalogram (EEG) and evoked potential (EP) mapping system has been developed EEG and EP signals acquired from 32-channel electrodes attached on the heroid surface are amplified by a pre-amplifier which is separated from main amplifier and is located near the patient to reduce signal attenuation and noise contamination between electrodes and the amplifier. The amplified signals are further amplified by a main amplifier where various filtering and gain contr61 are achieved An automatic artifact rejection scheme is employed using neural network-based EEG and artifact classifier, by which examination time is substantially reduce4 The continuously measured EEG sigrlals are used for spectral mapping, and auditory and visual evoked potentials measured in synchronous to the auditory and visual stimuli are used for temporal evoked potential mapping. A user-friendly graphical interface based on the Microsoft Window 3.1 is developed for the operation of the system. Statistical databases for comparisons of group and individual are included to support a statistically-based diagnosis.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
• /
• pp.483-484
• /
• 2007

In this paper, we describe a chip design technique for instrumentation amplifier using a nested-chopping technique. Conventional chopping technique uses a pair of chopper, but nested chopping technique uses two pairs of chopper to reduce residual offset and 1/f noise. The inner chopper pair removes the 1/f noise, while the outer chopper pair reduces the residual offset. Our instrumentation amplifier using a nested chopping technique has residual offset under 100 nV. We also implement very low frequency filter. Since this filter needs very large RC time constant, we use a technique named 'diode connected PMOS' to increase R with small die area. The total power consumption is 3.1 mW at the supply voltage of 3.3V with the 0.35um general CMOS technology. The die area of implemented chip was $530um{\times}300um$.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2018년도 전력전자학술대회
• /
• pp.454-455
• /
• 2018

The impedance of an underwater acoustic transducers constituting a multi-channel array structure could be changed in real time by various transmission modes. A power amplifier for driving the transducers usually use a voltage control method, so the transducer and power amplifier may be damaged by over-power due to changeable load conditions. Therefore, the drive controller of the power amplifier should have the function of limiting the power. This paper propose the new voltage control method for limiting the driving power of transducers with variable impedance characteristics.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2007년도 하계학술대회 논문집
• /
• pp.271-273
• /
• 2007

본 논문에서는 TV나 Audio등에 사용되는 2채널 30W급 Class-D amplifier를 동부하이텍의 0.35um BD350BA 공정을 사용하여 디지털 방식의 Class-D amplifier 출력단 구동에 적합하도록 설계하였다. 출력단은 Bootstrap 전원을 사용한 N-N type의 30V LDMOS 내장형이며 각각 $250m{\Omega}$의 턴 온 저항을 갖게 설계 되었다. THD+N 특성개선을 위한 Dead time 및 Delay 조정회로를 내장하였으며 보호회로로는 Over current, Over temperature, UVLO 가 있다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제15권3호
• /
• pp.334-341
• /
• 2015

This research outlines the design of a HR-TDC (High Resolution Time-to-Digital Converter) for high data rate communication systems using a $0.18{\mu}m$ CMOS process. The coarse-fine architecture has been adopted to improve the resolution of the TDC. A two-stage vernier time amplifier (2S-VTA) was used to amplify the time residue, and the gain of the 2S-VTA was larger than 64. The error during time amplification was compensated using two FTDCs (Fine-TDC) with their outputs. The resolution of the HR-TDC was 0.15 ps with a 12-bit output and the power consumption was 4.32 mW with a 1.8-V supply voltage.

• 대한전자공학회논문지SD
• /
• 제39권2호
• /
• pp.56-62
• /
• 2002

문턱전압 스윙 드라이버(threshold voltage swing driver)와 이중 감지 증폭기 리시버(dual sense amplifier receiver)를 가진 새로군 고속 저전압 스윙 온 칩 버스 (on-chip BUS)를 제안하였다. 문턱전압 스윙 드라이버는 버스에서의 전압상승 시간을 CMOS 인버터(inverter) 드라이버에서의 약 30% 이내로 줄여주고, 이중 감지 증폭기 리시버는 감지 증폭기 리시버를 사용하는 기존의 저전압 스윙 버스들의 데이터 전송량을 두 배 향상시켜 준다. 문턱전압 스윙 드라이버와 이중 감지 증폭기 리시버를 모두 사용할 경우, 온 칩 버스에서 사용하는 기존의 CMOS 인버터와 비교하여 제안된 방식은 약 60%의 속도 증가와 75%의 소모전력 감소를 얻는다.