• Journal of the Optical Society of Korea
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• v.18 no.5
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• pp.531-537
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• 2014

Through-silicon vias (TSVs) are fine, deep holes fabricated for connecting vertically stacked wafers during three-dimensional packaging of semiconductors. Measurement of the TSV geometry is very important because TSVs that are not manufactured as designed can cause many problems, and measuring the critical dimension (CD) of TSVs becomes more and more important, along with depth measurement. Applying white-light scanning interferometry to TSV measurement, especially the bottom CD measurement, is difficult due to the attenuation of light around the edge of the bottom of the hole when using a low numerical aperture. In this paper we propose and demonstrate four bottom CD measurement methods for TSVs: the cross section method, profile analysis method, tomographic image analysis method, and the two-dimensional Gaussian fitting method. To verify and demonstrate these methods, a practical TSV sample with a high aspect ratio of 11.2 is prepared and tested. The results from the proposed measurement methods using white-light scanning interferometry are compared to results from scanning electron microscope (SEM) measurements. The accuracy is highest for the cross section method, with an error of 3.5%, while a relative repeatability of 3.2% is achieved by the two-dimensional Gaussian fitting method.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.79-84
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• 2010

Formation of TSV (Through-Si-Via) with an Au seed layer and Cu filling to the via, simplification of bumping process for three dimensional stacking of Si dice were investigated. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process using $SF_6$ and $C_4F_8$ plasmas alternately. The vias were 40 ${\mu}m$ in diameter, 80 ${\mu}m$ in depth, and were produced by etching for 1.92 ks. On the via side wall, a dielectric layer of $SiO_2$ was formed by thermal oxidation, and an adhesion layer of Ti, and a seed layer of Au were applied by sputtering. Electroplating with pulsed DC was applied to fill the via holes with Cu. The plating condition was at a forward pulse current density of 1000 mA/$dm^2$ for 5 s and a reverse pulse current density of 190 mA/$dm^2$ for 25 s. By using these parameters, sound Cu filling was obtained in the vias with a total plating time of 57.6 ks. Sn bumping was performed on the Cu plugs without lithography process. The bumps were produced on the Si die successfully by the simplified process without serious defect.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.17-20
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• 2003

The EMC's rheological effects on molding process are evaluated in this study. When considering mold processing for IC packages, the major concerning items in current studies are incomplete fill, severe wire sweeping and paddle shifts etc. To simulate EMC's fast curing rheokinetics with 3D mold flow behavior, one should select appropriate rheometry which characterize each EMC's rheological motion and finding empirical parameters for numerical analysis current studies present the new rheometry with parallel plate rheometry for reactive rheokinetic experiments, the experiment and numerical analysis is done with the commercial higher filler loaded EMC for the case of Thin Quad Plant Packages (TQFP) with package thickness below 1.0 mm. The experimental results and simulation results based on new rheometry matches well in point of the prediction of wire sweep, filling behavior of melt front advancement and void trapping position.

• Korean Journal of Materials Research
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• v.14 no.6
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• pp.443-450
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• 2004

Parylene polymer thin film shows excellent homogeneous coverage chracteristics when it was deposited onto very complex three dimensional solid matters, such as deep hole and micro crack. The parylene deposition process can be conducted at room temperature although most of chemical vapor deposition processes request relatively high processing temperature. Therefore, the parylene coating process does not induce any thermal problems. Parylene thin film is transparent and has extremly high chemical stability. For example, it shows high chemical stability with high reactive chemical solutions such as strong acid, strong alkali and acetone. The bio-stability of this material gives good chances to use for a packaging of biomedical devices and electronic devices such as display. In this review article, principle of deposition process, properties and application fields of parylene polymer thin film are introduced.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.1975-1984
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• 1997

In this paper, we analyzed the frequency characteristics and the crosstalk of the adjacent parallel lines and the crossed lines in high-speed packaging interconnections by using the three-dimensional finite difference time domain (3D FDTD) method. To analyze the actual crosstalk phenomena in the transmission of the high-speed digital sgnal, the step pulse with fast rise time was used for the source excitation signal instead of using the Gaussian pulse that is generally used in FDTD. To veify the theoretical resutls, the experimental interconnection lines that were fabricated on the Duroid substrate($\varepsilon_{r}$=2.33, h=0.787 [mm]) were tested by TDR(time domain reflectometry). The results show good agreement between the analyzed results and the tested outcomes.

• Korean Journal of Metals and Materials
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• v.48 no.7
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• pp.667-673
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• 2010

Copper filling into TSV (through-silicon-via) and reduction of the filling time for the three dimensional chip stacking were investigated in this study. A Si wafer with straight vias - $30\;{\mu}m$ in diameter and $60\;{\mu}m$ in depth with $200\;{\mu}m$ pitch - where the vias were drilled by DRIE (Deep Reactive Ion Etching) process, was prepared as a substrate. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to reduce the time required complete the Cu filling into the TSV, the PPR (periodic pulse reverse) wave current was applied to the cathode of a Si chip during electroplating, and the PR (pulse-reverse) wave current was also applied for a comparison. The experimental results showed 100% filling rate into the TSV in one hour was achieved by the PPR electroplating process. At the interface between the Cu filling and Ti/ Au functional layers, no defect, such as a void, was found. Meanwhile, the electroplating by the PR current showed maximum 43% filling ratio into the TSV in an hour. The applied PPR wave form was confirmed to be effective to fill the TSV in a short time.

• Korean Journal of Metals and Materials
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• v.49 no.5
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

• Journal of Korean Institute of Industrial Engineers
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• v.26 no.3
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• pp.257-264
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• 2000

This research suggested a method by which the driver space can be designed to best accommodate the driver's anthropometric characteristics. Three-dimensional manikins and a variable seating buck were developed and used for this study. Manikins were designed with 18 links comprising the 95th percentile male and 5th percentile female data. The seating buck was built to create various driving environments using the distance and the height between the H-point(hip pivot) of the seat and the AHP(accelerator heel point), the angle of the back rest, the angle of the steering wheel, the vertical distance of the steering wheel, and the location of the T.G.S.(transmission gear shift) knob. Measurements of each variable were collected with a coordinate measuring machine by positioning the 3-D manikin under various combinations of the design factors of the seating buck, which was constructed based on mid-size domestic passenger cars. The data were then converted to the joint angles of the driver. The combination of the measurements for an optimal driving environment is suggested by applying sets of the joint angles at which the driver feels comfortable.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.1-9
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• 2010

Three-dimensional (3-D) integration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip to form highly integrated micro-nano systems. Since CMOS device scaling has stalled, 3D integration technology allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. The potential benefits of 3D integration can vary depending on approach; increased multifunctionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. It is expected that the semiconductor industry's paradiam will be shift to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D based technologies in highly integrated systems. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of IT-NT-BT systems. This paper attempts to introduce new 3D integration technologies of the chip self-assembling stacking and 3D heterogeneous opto-electronics integration for realizng the super-chip.

• Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
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• v.3 no.3
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• pp.231-236
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• 2005

HIC transport packaging to transport a high integrity container(HIC) containing dry spent resin generated from nuclear power plants is to comply with the regulatory requirements of Korea and IAEA for Type B packaging due to the high radioactivity of the content, and to maintain the structural integrity under normal and accident conditions. It must withstand 9 m free drop impact onto an unyielding surface and 1 m drop impact onto a mild steel bar in a position causing maximum damage. For the conceptual design of a cylindrical HIC transport package, three dimensional dynamic structural analysis to ensure that the integrity of the package is maintained under all credible loads for 9 m free drop and 1 m puncture conditions were carried out using ABAQUS code.