• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.12
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• pp.1039-1044
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• 2002

Film Bulk Acoustic Resonator (FBAR) using thin piezoelectric films can be made as monolithic integrated devices with compatibility to semiconductor process, leading to small size, low cost and high Q RF circuit elements with wide applications in communications area. This paper presents an MMIC compatible suspended FBAR using SOI micromachining. It is possible to make a single crystal silicon membrane using a SOI wafer In fabricating active devices, SOI wafer offers advantage which removes the substrate loss. FBAR was made on the 12㎛ silicon membrane. Electrode and Piezoelectric materials were deposited by RF magnetron sputter. The maximum resonance frequency of FBAR was shown at 2.5GHz range. The reflection loss, K$^2$$\_$eff/, Q$\_$serise/ and Q$\_$parallel/ in that frequency were 1.5dB, 2.29%, 220 and 160, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05b
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• pp.31-34
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• 2003

The sapphire wafers for blue light emitting devices were manufactured by the implementation of the surface machining technology based on micro-tribology. This process has been performed by chemical and mechanical polishing(CMP) process. The sapphire crystalline wafers were characterized by double crystal X-ray diffraction. The sample quality of sapphire crystalline wafer at surfaces has a full width at half maximum 89 arcses. The surfaces of sapphire wafers were mechanically affected by residual stress and surface default. Sapphire wafers's waveness has higher abrasion rate in the edge of the wafer than its center due to Newton's Ring interference.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.383-385
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• 2013

반도체소자의 고속실현을 위해서 알루미늄배선에서 40% 가량 성능을 높이는 반면 제조비용은 30%까지 낮출 수 있는 구리를 선호하고 있으나, 식각이 잘 되지 않아 원하는 패턴으로 만들어 내기가 곤란한 공정기술의 어려움과 구리물질이 지닌 유독성문제를 가지고 있다. 기존의 식각기술로는 구리패턴을 얻을 수 없는 기술적 한계 때문에 화학.기계적 연마(CMP)를 이용한 평탄화와 연마를 통해서 구리배선을 얻는 다마스커스(Damascene)기술이 개발됐고 이를 이용한 구리배선기술이 현실적으로 가능하게 됐다. CMP를 이용한 평탄화 및 연마 공정에서 Wafer에 도포된 구리의 두께를 실시간으로 측정하여 정밀하게 제어할필요가 있는데, 본 논문에서는 와전류를 이용하여 옹고스트롬 단위의 두께를 실시간으로 측정하여 제어 하는 시스템구현에 대해 기술한다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.86-87
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• 2007

The dispersive method of white-light interferometry is proper for in-line 3-D inspection of dielectric thin-film thickness to be used in the semiconductor and flat-panel display industry. This research is the measurement application of CMP patterned wafer. The results describe 3-D and 2-D profile of the step height during polishing time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.250-251
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• 2005

Tin dioxide (SnO$_2$) thin films have been prepared on Si wafer (100) by Plasma Enhanced Chemical Vapor Deposition (PECVD). SnO$_2$ thin films were prepared from mixtures of dibutyltin diacetate as a precursor, oxygen as an oxidant at 275, 325, 375, 425$^{\circ}C$, respectively. The microstructure of deposited films was characterized by X-ray diffraction and field emission scanning electron microscopy. Structural characteristics of prepared SnO$_2$ thin films were investigated with different substrate temperature. The deposition rate was linearly increased with substrate temperature. Surface morphology and uniformity of prepared thin film was excellent at 375$^{\circ}C$ and grain size was averagely 25nm.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.5
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• pp.410-416
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• 2001

KLN thin films were fabricated on Pt coated Si(100) wafer using an rf-magnetron sputtering method. The grown KLN thin film consists of 4-fold grains. In this experiment, the structure of 4-fold grained thin film was investigated using XRD and SEM measurements. Pt layer was also deposited using the rf-magnetron sputtering method,. XRD measurement showed that he Pt thin film has Gaussian distribution form with strong (111) direction orientation. The KLN thin film has preferred-orientation of (001) direction, and the peak consists of 2 separate peaks; one with broad FWHM and the other with narrow FWHM. The sharp peak is due to single crystal, and combining with Em results, the 4-fold grain consists of singel crystals with c-axis normal to substrate.

• Journal of the Semiconductor & Display Technology
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• v.15 no.3
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• pp.57-61
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• 2016

We have studied the structural, optical and electrical properties of IGZO thin films. The IGZO thin films were deposited on the silicon wafer by RF magnetron sputtering method. The RF power in sputtering process was varied as 15W, 30W, 45W, 60W, 75W, respectively. All of the thin films transmittance in the visible range was above 85%. XRD analysis showed that amorphous structure of the thin films without any peak. The Hall measurements in the low RF power is the high mobility above $10cm^2/V{\cdot}s$ and the low resistvity are obtained in the IGZO thin films.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.189.1-189.1
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• 2013

Titanium dioxide (TiO2) is a wide bandgap semiconductor possessing photochemical stability and thus widely used for photocatalysis. However, enhancing photocatalytic efficiency is still a challenging issue. In general, the efficiency is affected by physio-chemical properties such as crystalline phase, crystallinity, exposed crystal facets, crystallite size, porosity, and surface/bulk defects. Here we propose an alternative approach to enhance the efficiency by studying interfaces between thin TiO2 layers to be stacked; that is, the interfacial phenomena influencing on the formation of porous structures, controlling crystallite sizes and crystallinity. To do so, multi-layered TiO2 thin films were fabricated by using a sol-gel method. Specifically, a single TiO2 thin layer with a thickness range of 20~40 nm was deposited on a silicon wafer and annealed at $600^{\circ}C$. The processing step was repeated up to 6 times. The resulting structures were characterized by conventional electron microscopes, and followed by carrying out photocatalytic performances. The multi-layered TiO2 thin films with enhancing photocatalytic efficiency can be readily applied for bio- and gas sensing devices.

• Mass Spectrometry Letters
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• v.12 no.1
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• pp.26-30
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• 2021

The impurity concentration is a crucial parameter for semiconductor thin films. Evaluating the impurity distribution in silicon thin film is another challenge. In this study, we have investigated the doping concentration of boron in silicon thin film using time of flight secondary ion mass spectrometry in dynamic mode of operation. Boron doped silicon film was grown on i) p-type silicon wafer and ii) borosilicate glass using hot wire chemical vapor deposition technique for possible applications in optoelectronic devices. Using well-tuned SIMS measurement recipe, we have detected the boron counts 101~104 along with the silicon matrix element. The secondary ion beam sputtering area, sputtering duration and mass analyser analysing duration were used as key variables for the tuning of the recipe. The quantitative analysis of counts to concentration conversion was done following standard relative sensitivity factor. The concentration of boron in silicon was determined 1017~1021 atoms/㎤. The technique will be useful for evaluating distributions of various dopants (arsenic, phosphorous, bismuth etc.) in silicon thin film efficiently.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.41-45
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• 2018

As the size of semiconductor chip shrinks, the electronic industry has been paying close attention to fan-out wafer level packaging (FO-WLP) as an emerging solution to accommodate high input and output density. FO-WLP also has several advantages, such as thin thickness and good thermal resistance, compared to conventional packaging technologies. However, one major challenge in current FO-WLP manufacturing process is to control wafer warpage, caused by the difference of coefficient of thermal expansion and Young's modulus among the materials. Wafer warpage induces misalignment of chips and interconnects, which eventually reduces product quality and reliability in high volume manufacturing. In order to control wafer warpage, it is necessary to understand the effect of material properties and design parameters, such as chip size, chip to mold ratio, and carrier thickness, during packaging processes. This paper focuses on the effects of thickness of chip and molding compound on 12" wafer warpage after PMC of EMC using finite element analysis. As a result, the largest warpage was observed at specific thickness ratio of chip and EMC.