• 반도체디스플레이기술학회지
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• 제12권4호
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• pp.39-44
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• 2013

In the semiconductor heat-treatment process, the temperature uniformity determines the film quality of a wafer. This film quality effects on the overall yield rate. The heat transfer of the wafer surface in the heat-treatment process equipment is occurred by convection and radiation complexly. Because of this, there is the nonlinearity between the wafer temperature and reactor. Therefore, the accurate prediction of temperature on the wafer surface is difficult without the direct measurement. The thermal camera and the T/C wafer are general ways to confirm the temperature uniformity on the heat-treatment process. As above ways have limit to measure the temperature in the precise domain under the micro-scale. In this study, we developed the thin film type temperature sensor using the MEMS technology to establish the system which can measure the temperature under the micro-scale. We combined the experiment and numerical analysis to verify and calibrate the system. Finally, we measured the temperature on the wafer surface on the semiconductor process using the developed system, and confirmed the temperature variation by comparison with the commercial T/C wafer.

• 대한기계학회논문집A
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• 제28권1호
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• pp.85-91
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• 2004

The sapphire wafers for blue light emitting devices were manufactured by the implementation of the surface machining technology based on micro-tribology. This process has been performed by chemical and mechanical polishing process. The sapphire crystalline wafers were characterized by double crystal X-ray diffraction. The sample quality of sapphire crystalline wafer at surfaces has a full width at half maximum of 89 arcsec. The surfaces of sapphire wafer were mechanically affected by residual stress during the polishing process. The wave pattern of optical interference of sapphire wafer implies higher abrasion rate in the edge of the wafer than its center from the Newton's ring.

• 한국결정성장학회지
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• 제10권5호
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• pp.350-355
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• 2000

수평 Bridgeman방식으로 성장된 C축 방향의 사파이어 결정기판을 연마 가공하였으며, 또한 유기금속 기상화학 증착 방법으로 사파이어 기판 위에 GaN 박막을 증착하였다. 사파이어 인고트를 성장하여 2인치 사파이어 기판으로 이용하였으며 웨이퍼 절편장치 및 연마장치를 개발하였다. 이러한 다단계의 연마 가공은 기판 표면을 경면화하였다. 표면 평탄도 및 조도는 원자힘현미경으로 측정하였다. 개발된 사파이어 기판위에 성장된 GaN 박막의 특성 및 청색광소자로의 응용 가능성을 확인하였다.

• 한국세라믹학회지
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• 제36권8호
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• pp.863-870
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• 1999

SOI(silicon on insulafor) was fabricated through the direct bonding using (100) Si wafer and 4$^{\circ}$off (100) Si wafer to investigate the stacking faults in silicon at the Si/SiO2 oxidized and bonded interface. The treatment time of wafer surface using MSC-1 solution was varied in order to observe the effect of cleaning on bonding characteristics. As the MSC-1 treating time increased surface hydrophilicity was saturated and surface microroughness increased. A comparison of surface hydrophilicity and microroughness with MSC-1 treating time indicates that optimum surface modified condition for time was immersed in MSC-1 for 2 min. The SOI structure directly bonded using (100) Si wafer and 4$^{\circ}$off (100) Si wafer at the room temperature were annealed at 110$0^{\circ}C$ for 30 min. Then the stacking faults at the bonding and oxidation interface were examined after the debonding. The results show that there were anomalies in the gettering of the stacking faults at the bonded region.

• 한국진공학회:학술대회논문집
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• 한국진공학회 1998년도 제16회 학술발표회 논문개요집
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• pp.93-93
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• 1998

• 한국재료학회지
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• 제28권12호
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• pp.709-713
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• 2018

To improve the etch rate of $Si_3N_4$ thin film, $H_2SiF_6$ is added to increase etching rate by more than two times. $SiO_3H_2$ is gradually added to obtain a selectivity of 170: 1 at 600 ppm. Moreover, when $SiO_3H_2$ is added, the etching rate of the $SiO_2$ thin film increases in proportion to the radius of the wafer. In $Si_3N_4$ thin film, there is no difference in the etching rate according to the position. However, in the $SiO_2$ thin film, the etching rate increases in proportion to the radius. At the center of the wafer, the re-growth phenomenon is confirmed at a specific concentration or above. The difference in etch rates of $SiO_2$ thin films and the reason for regrowth at these positions are interpreted as the result of the flow rate of the chemical solution replaced with fresh solution.

• 센서학회지
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• 제1권2호
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• pp.131-145
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• 1992

본 논문은 SOI트랜스듀서 및 회로를 위해, Si 직접접합과 M-C국부연마법에 의한 박막SOI구조의 형성 공정을 기술한다. 또한, 이러한 박막SOI의 전기적 및 압저항효과 특성들을 SOI MOSFET와 cantilever빔으로 각각 조사했으며, bulk Si에 상당한다는 것이 확인되었다. 한편, SOI구조를 이용한 두 종류의 압력트랜스듀서를 제작 및 평가했다. SOI구조의 절연층을 압저항의 유전체분리층으로 이용한 압력트랜스듀서의 경우, $-20^{\circ}C$에서 $350^{\circ}C$의 온도범위에 있어서 감도 및 offset전압의 변화는 자각 -0.2% 및 +0.15%이하였다. 한편, 절연층을 etch-stop막으로 이용한 압력트랜스듀서에 있어서의 감도변화를 ${\pm}2.3%$의 표준편차 이내로 제어할 수 있다. 이러한 결과들로부터 개발된 SDB공정으로 제작된 SOI구조는 집적화마이크로트랜스듀서 및 회로개발에 많은 장점을 제공할 것이다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1998년도 추계학술발표강연 및 논문개요집
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• pp.27-27
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• 1998

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 Proceedings of 6th International Joint Symposium on Microeletronics and Packaging
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• pp.49-56
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• 2001

• 한국태양에너지학회 논문집
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• 제32권spc3호
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• pp.194-198
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• 2012

Crystalline silicon solar cell remains the major player in the photovoltaic marketplace with 80% of the market, despite the development of various thin film technologies. Silicon's excellent efficiency, stability, material abundance and low toxicity have helped to maintain its position of dominance. However, the cost of silicon materials remains a major barrier to reducing the cost of silicon photovoltaics. Using the crystalline silicon wafer with thinner thickness is the promising way for cost and material reduction in the solar cell production. However, the thinner the silicon wafer is, the worse bow phenomenon is induced. The bow phenomenon is observed when two or more layers of materials with different temperature expansion coefficiencies are in contact, in this case silicon and aluminum. In this paper, the solar cells were fabricated with different thicknesses of Al layer in order to reduce the bow phenomenon. With less amount of paste applications, we observed that the bow could be reduced by up to 40% of the largest value with 120 micron thickness of the wafer even though the conversion efficiency decrease by 0.5% occurred. Since the bowed wafers lead to unacceptable yield losses during the module construction, the reduction of bow is indispensable on thin crystalline silicon solar cell. In this work, we have studied on the counterbalance between the bow and conversion efficiency and also suggest the formation of enough back surface field (BSF) with thinner Al layer application.