• Korean Journal of Materials Research
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• v.9 no.2
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• pp.124-131
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• 1999

Copper film, which is expected to be used as interconnection material for 1 giga DRAM integrated circuits was deposited on hole and trench patterns by Metal Organic Chemical Vapor Deposition(MOCVD) method. After a reflow process, contact and L/S patterns were filled by copper and the characteristics of the Cu reflow process were investigated. When deposited Cu films were reflowed, grain growth and agglomeration of Cu have occurred in surfaces and inner parts of patterns as well as complete filling in patterns. Also Cu thin oxide layers were formed on the surface of Cu films reflowed in $O_2$ambient. Agglomeration and oxidation of Cu had bad influence on the electrical properties of Cu films especially, therefore, their removal and prevention were studied simultaneously. As a pattern size is decreased, preferential reflow takes place inside the patterns and this makes advantages in filling patterns of deep submicron size completely. With Cu reflow process, we could fill the patterns with the size of deep sub-micron and it is expected that Cu reflow process could meet the conditions of excellent interconnection for 1 giga DRAM device when it is combined with Cu MOCVD and CMP process.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.4 s.37
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• pp.345-349
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• 2005

Low resistive ($300{\mu}{\Omega}$-cm) W-C-N films have been deposited on tetraethylorthosilicate (TEOS) interlayer dielectric by atomic layer deposition (ALD) with $WF_6-N_2-CH_4$ gas. The exposure cycles of $N_2$ and $CH_4$ are synchronized with pulse plasma. The W-C-N films on TEOS layer follow the ALD mechanism and keep constant deposition rate of 0.2 nm/cycle from 10 to 100 cycles. As a diffusion barrier for Cu interconnection the W-C-N films maintain amorphous phase and Cu inter-diffusion is not occurred even at $800^{\circ}C$ for 30 min.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.181-184
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• 2002

This paper describes fabrication and characteristics of ceramic pressure sensor for working at high temperature. The proposed pressure sensor consists of a Ta-N thin-film, patterned on a Wheatstone bridge configuration, sputter deposited onto thermally oxidized Si membranes with an aluminium interconnection layer. The fabricated pressure sensor presents a low temperature coefficient of resistance, high sensitivity, low non-linearity and excellent temperature stability The sensitivity is 1.097∼1.21 mV/V$.$kgf/$\textrm{cm}^2$ in the temperature range of 25∼200$^{\circ}C$ and the maximum non-linearity is 0.43 %FS.

• Journal of the Semiconductor & Display Technology
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• v.4 no.3 s.12
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• pp.17-22
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• 2005

LED lamp was designed by the serial-parallel integration of LED chips in metal-interconnection. The 7 $4.5{\times}4.5\;in^{2}$ masks were designed with the contact type of chrome-no mirror?dark. The white epitaxial thin film was grown by metal-organic chemical vapor deposition. The active layers were consisted with the serial order of multi-quantum wells for blue, green and red lights. The fabricated LED chip showed the electroluminescence peaked at 450, 560 and 600 nm. For the current injection of 20 mA, the operating voltage was measured to 4.25 V and the optical emission power was obtained to 0.7 $\mu$W.

• Journal of the Korean institute of surface engineering
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• v.38 no.1
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• pp.28-36
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• 2005

In this study, the reflow characteristics of copper thin films which is expected to be used as interconnection materials in the next generation semiconductor devices were investigated. Cu thin films were deposited on the TaN diffusion barrier by metal organic chemical vapor deposition (MOCVD) and annealed at the temperature between 250℃ and 550℃ in various ambient gases. When the Cu thin films were annealed in the hydrogen ambience compared with oxygen ambience, sheet resistance of Cu thin films decreased and the breakdown of TaN diffusion barrier was not occurred and a stable Cu/TaN/Si structure was formed at the annealing temperature of 450℃. In addition, reflow properties of Cu thin films could be enhanced in H₂ ambient. With Cu reflow process, we could fill the trench patterns of 0.16～0.24 11m with aspect ratio of 4.17～6.25 at the annealing temperature of 450℃ in hydrogen ambience. It is expected that Cu reflow process will be applied to fill the deep pattern with ultra fine structure in metallization.

• Journal of the Korean Vacuum Society
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• v.10 no.1
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• pp.27-30
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• 2001

Electromigration Phenomena in Al-1%Si thin film interconnections under DC and PDC conditions were investigated. Thin film interconnections with $SiO_2$ and PSG/$SiO_2$ dielectric passivation layer were formed by a standard photolithography process method and test line lengths were 100, 400, 800, 1200, and 1600 $\mu\textrm{m}$. The current density of $1.19\times10^7\textrm{A/cm}^2$ was stressed in Al-1%Si thin film interconnections under DC condition. The current density of $1.19\times10^7\textrm{A/cm}^2$ was also applied under PDC condition at the frequency of 1 Hz with the duty factor of 0.5. The electromigration resistance of PSG/SiO2 dielectric passivation test line was stronger than $SiO_2$ dielectric passivation test line. The lifetime under PDC was 2-4 times longer than DC condition. As the thin film interconnection line increased, the lifetime decreased and saturated over the critical length. Failure patterns by an electromigration were dominated by void-induced electrical open and hillock-induced electrical short.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.93-100
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• 2003

The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. These latter technologies have not kept pace with the IC scaling trends, resulting in a so-called“interconnect technology gap”. Multilayer thin film technology is proposed as a“bridge”- technology between the very high density IC technology and the coarse standard PCB technology. It is also a key enabling technology for the realisation of true“System-in-a-Package”(SIP) solutions, combining multiple“System-on-a-Chip”(SOC) IC's with other components and also integrating passive components in its layers. A further step is to use this technology to realise new functionalities on top of active wafers. These additional“above-IC”processed layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.

• Korean Chemical Engineering Research
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• v.47 no.2
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• pp.141-149
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• 2009

The Cu thin film material and process, which have been already used for metallization of CMOS(Complementary Metal Oxide Semiconductor), has been highlighted as the Cu metallization is introduced to the metallization process for giga - level memory devices. The recent progresses in the development of key elements in electrochemical processes like surface pretreatment or electrolyte composition are summarized in the paper, because the semiconductor metallization by electrochemical processes such as electrodeposition and electroless deposition controls the thickness of Cu film in a few nm scales. The technologies in electrodeposition and electroless deposition are described in the viewpoint of process compatibility between copper electrodeposition and damascene process, because a Cu metal line is fabricated from the Cu thin film. Silver metallization, which may be expected to be the next generation metallization material due to its lowest resistivity, is also introduced with its electrochemical fabrication methods.

• Journal of the Korean institute of surface engineering
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• v.28 no.3
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• pp.174-181
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• 1995

Multilayered silicon cantilever beams as interconnection systems for bare chip burn-in socket applications have been designed, fabricated and characterized. Fabrication processes of the beam are employing standard semiconductor processes such as thin film processes and epitaxial layer growth and silicon wet etching techniques. We investigated silicon etch rate in 1-3-10 etchant as functions of doping concentration, surface mechanical stress and crystal defects. The experimental results indicate that silicon etch rate in 1-3-10 etchant is strong functions of doping concentration and crystal defect density rather than surface mechanical stress. We suggested the new fabrication processes of multilayered silicon cantilever beams.

• Journal of the Korean Vacuum Society
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• v.5 no.3
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• pp.229-238
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• 1996

The electromigration phenomena and the characterizations of the conductor lifetime (Time-To-Failure, TTF) in Al-1%Si thin film interconnections under D.C. and Pulsed D.C. conditions were investigated . Meander type test patterns were fabricated with the dimensions of 21080$mu \textrm{m}$ length, 3$\mu\textrm{m}$ width, 0.7$\mu\textrm{m}$ thickness and the 0.1$\mu\textrm{m}$/0.8$\mu\textrm{m}$($SiO_2$/PSG)dielectric overlayer. The current densities of $2 \times10^6 A/\textrm{cm}^2$ and $1 \times10^7 A/\textrm{cm}^2$ were stressed in Al-1%Si thin film interconnection s under a D.C. condition. The peak current densities of $2 \times10^6 A/\textrm{cm}^2$ and $1 \times10^7 A/\textrm{cm}^2$ were also applied under a Pulsed D.C. condition at frequencies of 200KHz, 800KHz, 1MHz, and 4MHz with the duty factor of 0.5. THe time-to-failure under a Pulsed D.C.($TTF_{pulsed D.C}$) was appeared to be larger than that under a D.C. condition. It was found that the TTF under both a D.C. and a Pulsed D.C. condition. It was found that the TTF under both a D.C. and a Pulsed D.C. condition largely depends upon the appiled current densities respectively . This can be explained by a relaxation mechanism view due to a duty cycle under a Pulsed D.C. related to the wave on off. The relaxation phenomena during the pulsed off period result in the decayof excess vacancies generated in the Al-1%Si thin film interconnections because of the electrical and mechanical stress gradient . Hillocks and voids formed by an electromigration were observed by using a SEM (Scanning Electron Microscopy).