• 한국재료학회지
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• 제9권2호
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• pp.124-131
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• 1999

Copper film, which is expected to be used as interconnection material for 1 giga DRAM integrated circuits was deposited on hole and trench patterns by Metal Organic Chemical Vapor Deposition(MOCVD) method. After a reflow process, contact and L/S patterns were filled by copper and the characteristics of the Cu reflow process were investigated. When deposited Cu films were reflowed, grain growth and agglomeration of Cu have occurred in surfaces and inner parts of patterns as well as complete filling in patterns. Also Cu thin oxide layers were formed on the surface of Cu films reflowed in $O_2$ambient. Agglomeration and oxidation of Cu had bad influence on the electrical properties of Cu films especially, therefore, their removal and prevention were studied simultaneously. As a pattern size is decreased, preferential reflow takes place inside the patterns and this makes advantages in filling patterns of deep submicron size completely. With Cu reflow process, we could fill the patterns with the size of deep sub-micron and it is expected that Cu reflow process could meet the conditions of excellent interconnection for 1 giga DRAM device when it is combined with Cu MOCVD and CMP process.

• 마이크로전자및패키징학회지
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• 제12권4호통권37호
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• pp.345-349
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• 2005

300 mW-cm의 낮은 비저항을 갖는 카본-질소$\_$텅스텐 (W-C-N) 확산방지막을 원자층 증착법으로 제조하였으며, 반응기체로 $WF_6-N_2-CH_4$를 사용하였다. $N_2$ 및 $CH_4$ 반응기체를 주입 할 때는 고주파 펄스를 인가하여 플라즈마에 의한 반응물의 분리가 일어나도록 하였다. 다층금속배선에 사용하는 층간 절연층 (TEOS) 위에서 W-C-N 박막은 원자층 증착기구를 따르며, 10에서 100 사이클 동안 증착율이 0.2nm/cycles 로 일정한 값을 가진다. 또한 Cu 배선을 위한 확산방지막으로써 W-C-N 박막은 비정질 상을 가지며, $800^{\circ}C$에서 30분간 열처리해도 Cu의 확산을 충분히 방지할 수 있음을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.181-184
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• 2002

This paper describes fabrication and characteristics of ceramic pressure sensor for working at high temperature. The proposed pressure sensor consists of a Ta-N thin-film, patterned on a Wheatstone bridge configuration, sputter deposited onto thermally oxidized Si membranes with an aluminium interconnection layer. The fabricated pressure sensor presents a low temperature coefficient of resistance, high sensitivity, low non-linearity and excellent temperature stability The sensitivity is 1.097∼1.21 mV/V$.$kgf/$\textrm{cm}^2$ in the temperature range of 25∼200$^{\circ}C$ and the maximum non-linearity is 0.43 %FS.

• 반도체디스플레이기술학회지
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• 제4권3호
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• pp.17-22
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• 2005

LED lamp was designed by the serial-parallel integration of LED chips in metal-interconnection. The 7 $4.5{\times}4.5\;in^{2}$ masks were designed with the contact type of chrome-no mirror?dark. The white epitaxial thin film was grown by metal-organic chemical vapor deposition. The active layers were consisted with the serial order of multi-quantum wells for blue, green and red lights. The fabricated LED chip showed the electroluminescence peaked at 450, 560 and 600 nm. For the current injection of 20 mA, the operating voltage was measured to 4.25 V and the optical emission power was obtained to 0.7 $\mu$W.

• 한국표면공학회지
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• 제38권1호
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• pp.28-36
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• 2005

In this study, the reflow characteristics of copper thin films which is expected to be used as interconnection materials in the next generation semiconductor devices were investigated. Cu thin films were deposited on the TaN diffusion barrier by metal organic chemical vapor deposition (MOCVD) and annealed at the temperature between 250℃ and 550℃ in various ambient gases. When the Cu thin films were annealed in the hydrogen ambience compared with oxygen ambience, sheet resistance of Cu thin films decreased and the breakdown of TaN diffusion barrier was not occurred and a stable Cu/TaN/Si structure was formed at the annealing temperature of 450℃. In addition, reflow properties of Cu thin films could be enhanced in H₂ ambient. With Cu reflow process, we could fill the trench patterns of 0.16～0.24 11m with aspect ratio of 4.17～6.25 at the annealing temperature of 450℃ in hydrogen ambience. It is expected that Cu reflow process will be applied to fill the deep pattern with ultra fine structure in metallization.

• 한국진공학회지
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• 제10권1호
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• pp.27-30
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• 2001

절연보호막 처리된 Al-1%Si 박막배선에서 DC와 PDC 조건하에서의 Electromigration 현상에 관하여 조사하였다. $SiO_2$와 PSG/$SiO_2$ 절연보호막 층을 갖는 박막배선은 표준 사진식각 공정으로 제작되었고, 테스트라인 길이는 100, 400, 800, 1200, 1600 $\mu\textrm{m}$이다. Al-l%Si 박막배선에 고정된 전류밀도 $1.19\times10^7\textrm{A/cm}^2$의 DC와 duty factor가 0.5인 1Hz의 주파수에 고정된 전류밀도 $1.19\times10^7\textrm{A/cm}^2$의 PDC를 인가하였다. Electromigration 테스트에서 PSG/$SiO_2$ 절연보호막 시편의 Electromigration 저항성이 $SiO_2$ 절연보호막 시편보다 우수함을 알 수 있었다. PDC 에서 박막 배선의 수명이 DC 보다 2-4배 정도 길게 나타났으며, 박막 배선의 길이가 증가 할 수록 수명이 감소하다가 임계길이 이상에서 포화되는 경향을 보인다. Electromigration에 의한 결함 형태로는 전기적 개방을 야기시키는 보이드와 전기적 단락을 야기시키는 힐록이 지배적이다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.93-100
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• 2003

The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. These latter technologies have not kept pace with the IC scaling trends, resulting in a so-called“interconnect technology gap”. Multilayer thin film technology is proposed as a“bridge”- technology between the very high density IC technology and the coarse standard PCB technology. It is also a key enabling technology for the realisation of true“System-in-a-Package”(SIP) solutions, combining multiple“System-on-a-Chip”(SOC) IC's with other components and also integrating passive components in its layers. A further step is to use this technology to realise new functionalities on top of active wafers. These additional“above-IC”processed layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.

• Korean Chemical Engineering Research
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• 제47권2호
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• pp.141-149
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• 2009

초고속 연산용 CMOS(complementary Metal Oxide Semiconductor) 배선재료로 사용되고 있는 구리(Cu)가, 기가급 메모리 소자용 금속 배선 물질에도 사용이 시작되면서 구리 박막에 대한 재료 및 공정이 새로운 조명을 받고 있다. 반도체 금속 배선에 사용하는 수 nm 두께의 구리 박막의 형성에 전해도금(electrodeposition)과 무전해 도금(electroless deposition) 같은 전기화학적 방법을 이용하게 되어서 표면 처리, 전해액 조성과 같은 중요한 요소에 대한 최신 연구 동향을 요약하였다. 구리 박막에서 구리 배선을 제작하여야 하므로 새로운 패턴 기술인 상감기법이 도입되어, 구리도금과 상감기법과의 공정 일치성 관점에서 전해도금과 무전해 도금의 요소 기술에 대해 기술하였다. 구리보다 비저항이 낮아 차세대 소자용 배선에 있어서 적용이 예상되는 은(Ag)을 전기화학적 방법으로 금속 배선에 적용하는 최신 연구에 대하여도 소개하였다.

• 한국표면공학회지
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• 제28권3호
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• pp.174-181
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• 1995

Multilayered silicon cantilever beams as interconnection systems for bare chip burn-in socket applications have been designed, fabricated and characterized. Fabrication processes of the beam are employing standard semiconductor processes such as thin film processes and epitaxial layer growth and silicon wet etching techniques. We investigated silicon etch rate in 1-3-10 etchant as functions of doping concentration, surface mechanical stress and crystal defects. The experimental results indicate that silicon etch rate in 1-3-10 etchant is strong functions of doping concentration and crystal defect density rather than surface mechanical stress. We suggested the new fabrication processes of multilayered silicon cantilever beams.

• 한국진공학회지
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• 제5권3호
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• pp.229-238
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• 1996

The electromigration phenomena and the characterizations of the conductor lifetime (Time-To-Failure, TTF) in Al-1%Si thin film interconnections under D.C. and Pulsed D.C. conditions were investigated . Meander type test patterns were fabricated with the dimensions of 21080$mu \textrm{m}$ length, 3$\mu\textrm{m}$ width, 0.7$\mu\textrm{m}$ thickness and the 0.1$\mu\textrm{m}$/0.8$\mu\textrm{m}$($SiO_2$/PSG)dielectric overlayer. The current densities of $2 \times10^6 A/\textrm{cm}^2$ and $1 \times10^7 A/\textrm{cm}^2$ were stressed in Al-1%Si thin film interconnection s under a D.C. condition. The peak current densities of $2 \times10^6 A/\textrm{cm}^2$ and $1 \times10^7 A/\textrm{cm}^2$ were also applied under a Pulsed D.C. condition at frequencies of 200KHz, 800KHz, 1MHz, and 4MHz with the duty factor of 0.5. THe time-to-failure under a Pulsed D.C.($TTF_{pulsed D.C}$) was appeared to be larger than that under a D.C. condition. It was found that the TTF under both a D.C. and a Pulsed D.C. condition. It was found that the TTF under both a D.C. and a Pulsed D.C. condition largely depends upon the appiled current densities respectively . This can be explained by a relaxation mechanism view due to a duty cycle under a Pulsed D.C. related to the wave on off. The relaxation phenomena during the pulsed off period result in the decayof excess vacancies generated in the Al-1%Si thin film interconnections because of the electrical and mechanical stress gradient . Hillocks and voids formed by an electromigration were observed by using a SEM (Scanning Electron Microscopy).