• 한국압력기기공학회 논문집
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• 제10권1호
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• pp.90-95
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• 2014

Local wall thinning is a point of concern in almost all steel structures such as pipe lines covered with a thermal insulator made up of materials with low thermal conductivity(fiberglass or mineral wool); hence, Non Destructive Technique(NDT) methods that are capable of detecting the wall thinning and defects without removing the insulation are necessary. In this study we developed a Pulsed Eddy Current(PEC) system to detect the wall thinning of Ferro magnetic steel pipes covered with fiber glass thermal insulator and shielded with Aluminum plate. The developed system is capable of detecting the wall thickness change through an insulation of thickness 10cm and 0.4mm aluminum shielding. In order to confirm the thickness change due to wall thinning, two different sensors, a hall sensor and coil sensor were used as a detecting element. In both cases, the results show a very good change corresponding to the thickness change of the test specimen. During these experiments a carbon steel tube of diameter 210mm and a length of 620mm, which is covered with insulator of 95mm thickness was used. To simulate the wall thinning, the thickness of the tube is changed for a specified length such as 2.5mm, 5mm and 8 mm from the inner surface of the tube. A 0.4mm thick Aluminum plate was covered on the Test specimen to simulate the shielding of the insulated pipelines. For both hall sensor and coil detection methods Fast Fourier transform(FFT) was calculated using window approach and the results for the test specimen without Aluminum shielding were summarized which shows a clear identification of thickness change in the test specimen by comparing the magnitude spectra. The PEC system can detect the wall thinning under the 95 mm thickness insulation and 0.4 mm Al shielding, and the output signal showed linear relation with tube wall thickness.

• Journal of Information Display
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• 제10권4호
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• pp.202-205
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• 2009

An automated circuit repair system was developed for enhancing the yield of nondefective liquid crystal panels, focusing on the resist patterns on the circuit material layer of thin-film transistor (TFT) substrates prior to etching. The developed system has an advantage over the parallel conventional system: In the former, the repair conditions depend on the type of resist whereas in the latter, the repair parameters must be fine-tuned for each circuit material. The developed system consists of a resist pattern defect inspection system and a pattern repair system for short and open defects. The repair system performs fine corrections of abnormal areas of the resist pattern. The open-repair system is equipped with a syringe to dispense resist. To maintain a stable resist diameter, a thermal insulator was installed in the syringe system. As a result, the diameter of the dispensed resist became much more stable than when no thermal insulator was used. The resist diameter was kept within the target of $400{\pm}100{\mu}m$. Furthermore, a prototype system was constructed, and using a dummy pattern, it was confirmed that the system worked automatically and correctly.

• 한국전기전자재료학회논문지
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• 제18권1호
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• pp.62-67
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• 2005

Recently, polymer insulators that are used for high voltage applications have some advantages such as light weight, small size, vandalism resistance, hydrophobicity and easy making process. During outdoor service of polymer insulators, the surface of the insulating material is frequently subjected to moisture and contamination that lead to dry band arcing. Their tracking resistance, erosion resistance, end sealing and shed design are very important because dry band arcing causes degradation of polymer surface. Aging test to estimate life property of polymer insulator is executed through several international standard such as IEC 61109 and CEA tracking wheel test, but is not getting clear conclusion yet. There are two methods in the diagnosis method of polymer insulator such as off-line and on-line. The diagnosis methods in off-line are external condition analysis by the eye, contaminant analysis on surface, surface analysis, pollution withstand voltage test, power frequency flashover voltage test, lightning impulse flashover test, tensile fracture load test and flexural load test. Polymer material is also investigated it's tracking resistance by adding surface active agent in IEC 587. In this paper, the tracking performance of polymer insulator with salt solution which is added surface active agent. The diagnosis of insulator sample has been analyzed by leakage current and visual examination, STRI guide and thermal image camera.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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• pp.239-242
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• 1998

Ca $F_2$ films have superior gate insulator properties than conventional gate insulator such as $SiO_2$, Si $N_{x}$, $SiO_{x}$, and T $a_2$ $O_{5}$ to the side of lattice mismatch between Si substrate and interface trap charge density( $D_{it}$). Therefore, this material is enable to apply Thin Film Transistor(TFT) gate insulator. Most of gate oxide film have exhibited problems on high trap charge density, interface state in corporation with O-H bond created by mobile hydrogen and oxygen atom. This paper performed Ca $F_2$ property evaluation as MIM, MIS device fabrication. Ca $F_2$ films were deposited at the various substrate temperature using a thermal evaporation. Ca $F_2$ films was grown as polycrystalline film and showed grain size variation as a function of substrate temperature and RTA post-annealing treatment. C-V, I-V results exhibit almost low $D_{it}$(1.8$\times$10$^{11}$ $cm^{-1}$ /le $V^{-1}$ ) and higher $E_{br}$ (>0.87MV/cm) than reported that formerly. Structural analysis indicate that low $D_{it}$ and high $E_{br}$ were caused by low lattice mismatch(6%) and crystal growth direction. Ca $F_2$ as a gate insulator of TFT are presented in this paper paperaper

• 한국전기전자재료학회논문지
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• 제14권3호
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• pp.228-233
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• 2001

This paper presents the optimized design, fabrication and thermal characteristics of micro-heaters for thermal MEMS (micro elelctro mechanical system) applications usign SOI (Si-on-insulator) and trench structures. The micro-heater is based on a thermal measurement principle and contains for thermal isolation regions a 10㎛ thick Si membrane with oxide-filled trenches in the SOI membrane rim. The micro-heater was fabricated with Pt-RTD (resistance thermometer device) on the same substrate by suing MgO as medium layer. The thermal characteristics of the micro-heater wit the SOI membrane is 280$\^{C}$ at input power 0.9W; for the SOI membrane with 10 trenches, it is 580$\^{C}$ due to reduction of the external thermal loss. Therefore, the micro-heater with trenches in SOI membrane rim provides a powerful and versatile alternative technology for improving the performance of micro-thermal sensors and actuators.

• 한국광학회:학술대회논문집
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• 한국광학회 2009년도 동계학술발표회 논문집
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• pp.541-542
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• 2009

We have developed an image reversal photoresist with high thermal stability and electric insulating properties for the single isolation structure of OLEDs. The thermal stability and electric insulating properties are investigated and compared with those of conventional insulator and cathode separator materials. The single isolation structure using the image reversal photoresist reduces the fabrication process steps and cuts down the manufacturing cost.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.140-140
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• 2009

The Metal-ferroelectric-semiconductor (MFS) structure has superior advantages such as high density integration and non-destructive read-out operation. However, to obtain the desired electrical characteristics of an MFS structure is difficult because of interfacial reactions between ferroelectric thin film and Si substrate. As an alternative solution, the MFS structure with buffer insulating layer, i.e. metal-ferroelectric-insulator-semiconductor (MFIS), has been proposed to improve the interfacial properties. Insulators investigated as a buffer insulator in a MFIS structure, include $Ta_2O_5$, $HfO_2$, and $ZrO_2$ which are mainly high-k dielectrics. In this study, we prepared the Dy-doped $La_2O_3$ solution buffer layer as an insulator. To form a Dy-doped $La_2O_3$ buffer layer, the solution was spin-coated on p-type Si(100) wafer. The coated Dy-doped $La_2O_3$ films were annealed at various temperatures by rapid thermal annealing (RTA). To evaluate electrical properties, Au electrodes were thermally evaporated onto the surface of the samples. Finally, we observed the surface morphology and crystallization quality of the Dy-doped $La_2O_3$ on Si using atomic force microscopy (AFM) and x-ray diffractometer (XRD), respectively. To evaluate electrical properties, the capacitance-voltage (C-V) and current density-voltage (J-V) characteristics of Au/Dy-doped La2O3/Si structure were measured.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2011년도 춘계학술대회 논문집
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• pp.1113-1114
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• 2011

• 한국재료학회:학술대회논문집
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• 한국재료학회 1998년도 IUMRS-ICEM ABSTRACT BOOK
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• pp.64.4-64
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• 1998

• 한국전기전자재료학회논문지
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• 제19권10호
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• pp.894-900
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• 2006

This paper reports the fabrication and characterization of $32{\times}32$ thermal cantilever array for nano-scaled memory device applications. The $32{\times}32$ thermal cantilever array with integrated tip heater has been fabricated with micro-electro-mechanical systems(MEMS) technology on silicon on insulator(SOI) wafer using 9 photo masking steps. All of single-level cantilevers(1,024 bits) have a p-n junction diode in order to eliminate any electrical cross-talk between adjacent cantilevers. Nonlinear electrical characteristic of fabricated thermal cantilever shows its own thermal heating mechanism. In addition, n-channel high-voltage MOSFET device is integrated on a wafer for embedding driver circuitry.